Static timing analysis of dynamically sensitizable paths

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Static timing analysis of dynamically sensitizable paths

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 568 - 573

Year of Publication: 1989

ISBN:0-89791-310-8

Authors

S. Perremans
L. Claesen
H. De Man

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 19

Additional Information:

abstract cited by index terms collaborative colleagues

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ABSTRACT

This paper describes a new method for solving the false path problem in static timing analysis of acyclic, combinational circuits. The conditions under which a path is false are accurately defined. The fact that these conditions explicitly take into account the dynamic behaviour of the circuit, constitutes the main contribution of the paper. An algorithm for computing the longest dynamically sensitizable paths in an acyclic, combinational circuit is presented.

CITED BY 19

	Hsi-Chuan Chen , David H. C. Du , Li-Ren Liu, Critical path selection for performance optimization, Proceedings of the 28th conference on ACM/IEEE design automation, p.547-550, June 17-22, 1991, San Francisco, California, United States
	Jengwei Pan , Larry Biro , Joel Grodstein , Bill Grundmann , Yao-Tsung Yen, Timing verification on a 1.2M-device full-custom CMOS design, Proceedings of the 28th conference on ACM/IEEE design automation, p.551-554, June 17-22, 1991, San Francisco, California, United States
	Edgar Bolender , Hans Martin Lipp, The exact solution of timing verification, Proceedings of the conference on European design automation, p.132-137, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Shiang-Tang Huang , Tai Ming Parng , Jyuo Min Shyu, A polynomial-time heuristic approach to approximate a solution to the false path problem, Proceedings of the 30th international conference on Design automation, p.118-122, June 14-18, 1993, Dallas, Texas, United States
	M. Ringe , T. Lindenkreuz , E. Barke, Path verification using Boolean satisfiability, Proceedings of the conference on Design, automation and test in Europe, p.965-966, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Li-Ren Liu , David H. C. Du , Hsi-Chuan Chen, An efficient parallel critical path algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.535-540, June 17-22, 1991, San Francisco, California, United States
	Patrick C. McGeer , Robert K. Brayton, Timing analysis in precharge/unate networks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.124-129, June 24-27, 1990, Orlando, Florida, United States
	V. Chandramouli , J. P. Whittemore , K. A. Sakallah, AFTA: a formal delay model for functional thinking analysis, Proceedings of the conference on Design, automation and test in Europe, p.350-355, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Hoon Chang , Jacob A. Abraham, VIPER: an efficient vigorously sensitizable path extractor, Proceedings of the 30th international conference on Design automation, p.112-117, June 14-18, 1993, Dallas, Texas, United States
	H. G. Yang , D. M. Holburn, A hierarchical approach to timing verification in CMOS VLSI design, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Provably correct high-level timing analysis without path sensitization, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.736-742, November 06-10, 1994, San Jose, California, United States
	Yun-Cheng Ju , Resve A. Saleh, Incremental techniques for the identification of statically sensitizable critical paths, Proceedings of the 28th conference on ACM/IEEE design automation, p.541-546, June 17-22, 1991, San Francisco, California, United States
	R. Peset Llopis, Exact path sensitization in timing analysis, Proceedings of the conference on European design automation, p.380-385, September 19-23, 1994, Grenoble, France
	P. Johannes , P. Das , L. Claesen , H. De Man, SLOCOP-II: a versatile timing verification system for MOSVLSI, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Jacques Benkoski , Ronald B. Stewart, TATOO: an industrial timing analyzer with false path elimination and test pattern generation, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	Kurt Keutzer , Sharad Malik , Alexander Saldanha, Is redundancy necessary to reduce delay, Proceedings of the 27th ACM/IEEE conference on Design automation, p.228-234, June 24-27, 1990, Orlando, Florida, United States
	Hoon Chang , Jacob A. Abraham, An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems, Journal of Electronic Testing: Theory and Applications, v.11 n.2, p.119-129, Oct. 1997
	Hakan Yalcin , John P. Hayes, Event propagation conditions in circuit delay computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.249-280, July 1997
	Lei Cheng , Deming Chen , Martin D. F. Wong , Mike Hutton , Jason Govig, Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California