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ABSTRACT
We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a Boolean function called the sensitization condition. We give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. We then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the LLLAMA timing environment. We give results on the IWLS and ISCAS benchmark examples and on carry-bypass adders.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
|
J. Benkoski, E. Vanden Meesch, L. Claesen, and H. De Man. Efficient Algorithms for Solving the False Path Problem in Timing Verification. In IEEE International Conference on Computer- Aided Design, 1987.
|
| |
2
|
Daniel Brand and Vijay S. Iyengar. Timing Anal ysis Using Functional Analysis. Technical Report RC 11768, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, 10598, 1986.
|
| |
3
|
R. K. Brayton, R. Rudell, A. L. Sagiovanni- Vincentelli, and A. Wang. Mis: a multiple-level logic optimization system. IEEE Teansactions on CAD, 1987.
|
| |
4
|
|
| |
5
|
|
| |
6
|
V. M. Hrapcenko. Depth and delay in a network. Soviet Math. DokL, 1978.
|
| |
7
|
N. J ouppi. TV: an nMOS Timing Analyzer. In Third Caltech VLSI Conference, 1983.
|
| |
8
|
S. Malik, A. R. Wang, R. K. Brayton, R. Rudell, and A. L. Sagiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In IEEE International Conference on Computer-Aided Design, 1988.
|
| |
9
|
|
| |
10
|
John K. Ousterhout. Crystal: a Timing Analyzer for nMOS VLSI Circuits. In Third Callech VI, SI Conference, 1983.
|
| |
11
|
J. P. Roth. Diagnosis of automata failures: a calculus and a method. IBM J. Res. Develop, 1966.
|
CITED BY 34
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Hsi-Chuan Chen , David H. C. Du , Li-Ren Liu, Critical path selection for performance optimization, Proceedings of the 28th conference on ACM/IEEE design automation, p.547-550, June 17-22, 1991, San Francisco, California, United States
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S. Kim , R. M. Owens , M. J. Irwin, Experiments with a performance driven module generator, Proceedings of the 29th ACM/IEEE conference on Design automation, p.687-690, June 08-12, 1992, Anaheim, California, United States
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Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States
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David Blaauw , Rajendran Panda , Abhijit Das, Removing user specified false paths from timing graphs, Proceedings of the 37th conference on Design automation, p.270-273, June 05-09, 2000, Los Angeles, California, United States
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Li-Ren Liu , David H. C. Du , Hsi-Chuan Chen, An efficient parallel critical path algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.535-540, June 17-22, 1991, San Francisco, California, United States
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S. W. Cheng , H.-C. Chen , D. H. C. Du , A. Lim, The role of long and short paths in circuit performance optimization, Proceedings of the 29th ACM/IEEE conference on Design automation, p.543-548, June 08-12, 1992, Anaheim, California, United States
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M. Kassab , E. Cerny , S. Aourid , T. Krodel, Propagation of last-transition-time constraints in gate-level timing analysis, Proceedings of the conference on Design, automation and test in Europe, p.796-802, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Shiang-Tang Huang , Tai Ming Parng , Jyuo Min Shyu, A polynomial-time heuristic approach to approximate a solution to the false path problem, Proceedings of the 30th international conference on Design automation, p.118-122, June 14-18, 1993, Dallas, Texas, United States
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Jing-Jia Liou , Angela Krstic , Li-C. Wang , Kwang-Ting Cheng, False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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V. Chandramouli , J. P. Whittemore , K. A. Sakallah, AFTA: a formal delay model for functional thinking analysis, Proceedings of the conference on Design, automation and test in Europe, p.350-355, February 23-26, 1998, Le Palais des Congrés de Paris, France
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M. Ringe , T. Lindenkreuz , E. Barke, Path verification using Boolean satisfiability, Proceedings of the conference on Design, automation and test in Europe, p.965-966, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Kurt Keutzer , Sharad Malik , Alexander Saldanha, Is redundancy necessary to reduce delay, Proceedings of the 27th ACM/IEEE conference on Design automation, p.228-234, June 24-27, 1990, Orlando, Florida, United States
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Lei Cheng , Deming Chen , Martin D. F. Wong , Mike Hutton , Jason Govig, Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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