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Efficient algorithms for computing the longest viable path in a combinational network
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 561 - 567  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
P. C. McGeer  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
R. K. Brayton  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 43,   Citation Count: 34
Additional Information:

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ABSTRACT

We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a Boolean function called the sensitization condition. We give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. We then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the LLLAMA timing environment. We give results on the IWLS and ISCAS benchmark examples and on carry-bypass adders.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J. Benkoski, E. Vanden Meesch, L. Claesen, and H. De Man. Efficient Algorithms for Solving the False Path Problem in Timing Verification. In IEEE International Conference on Computer- Aided Design, 1987.
 
2
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3
R. K. Brayton, R. Rudell, A. L. Sagiovanni- Vincentelli, and A. Wang. Mis: a multiple-level logic optimization system. IEEE Teansactions on CAD, 1987.
 
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V. M. Hrapcenko. Depth and delay in a network. Soviet Math. DokL, 1978.
 
7
N. J ouppi. TV: an nMOS Timing Analyzer. In Third Caltech VLSI Conference, 1983.
 
8
S. Malik, A. R. Wang, R. K. Brayton, R. Rudell, and A. L. Sagiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In IEEE International Conference on Computer-Aided Design, 1988.
 
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John K. Ousterhout. Crystal: a Timing Analyzer for nMOS VLSI Circuits. In Third Callech VI, SI Conference, 1983.
 
11
J. P. Roth. Diagnosis of automata failures: a calculus and a method. IBM J. Res. Develop, 1966.

CITED BY  34

Collaborative Colleagues:
P. C. McGeer: colleagues
R. K. Brayton: colleagues