| On the general false path problem in timing analysis |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 26th ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 555 - 560
Year of Publication: 1989
ISBN:0-89791-310-8
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Authors
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D. H. Du
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Department of Computer Science, University of Minnesota, Minneapolis, MN
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S. H. Yen
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Department of Computer Science, University of Minnesota, Minneapolis, MN
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S. Ghanta
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Department of Computer Science, University of Minnesota, Minneapolis, MN
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Downloads (6 Weeks): 13, Downloads (12 Months): 56, Citation Count: 24
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ABSTRACT
The false path problem is often referred to as the problem of detecting the longest sensitizable path (A path which is not a false path is a sensitizable path). The term “false path” is not clearly defined. In this paper, we first give a clear and precise definition of a false path. Then the general false path problem is formulated. The general false path problem is to detect whether a given path (not necessarily the longest one) is a false path. We present an efficient algorithm for solving the general false path problem. We also propose another algorithm which generates all the possible sensitizable paths with the delays greater than a given threshold T. The efficiency and effectiveness of the proposed algorithm are demonstrated by the experimental results.
Index Terms: Timing Verification, Logic Simulation, VLSI circuit, Timing Analysis, False path, Graph Theory.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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BELL88
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Design files provided by ATg~T Bell Labortory.
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BENK87
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Benkowski, J., Vanden Meersch, E., Claesen, L., and De Man, H. "Efficient Algorithms for Solving the False Path Problem in Timing Verification," Proceeding8 of ICCAD-SZ 44-47, 1987.
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BRAN86
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Brand, D. and Iyengar, V. S. "Timing Analysis Using Functional Relal~ionships," Proceeding8 of CCAD-86, 126-129, 1986; (See also "Timing Analysis using Functional Analysis" IBM Research Report, RC 11768(#52821) March 12th ~986.)
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HITC82a
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Hitchcock, R. B., Smith, G. L., and Cheng, D. D. "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, 1, January 1982, 100-105.
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HITC82b
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McWI80
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OUST85
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Ousterhout, J. K. "A Switch-Level Timing Verifier for Digital MOS VLSI," 1EF~E Transaction~ on Computer-Aided Design, Vol. CAD-4, 3, July 1985, 336-349.
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REDD86
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ROTH66
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J.P. Roth, "Diagnosis of automata failures: A calculus and a new method," IBM J. Res. Develop.,, OCT. 1966, pp. 278-281.
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SASA81
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Tohru Sasaki , Akihiko Yamada , Toshinori Aoyama , Katsutoshi Hasegawa , Shunichi Kato , Shinichi Sato, Hierarchical design verification for large digital systems, Proceedings of the 18th conference on Design automation, p.105-112, June 29-July 01, 1981, Nashville, Tennessee, United States
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SZYM86
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Szymanski, T. G. "LEADOUT: A Static Timing Analyzer for MOS Circuits," Proceeding8 of ICCAD-88, 130-133, 1986.
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YEN87
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Yen, H.C., Ghaaata, S., and Du, H C., "Timing Analysis Algorithms for Large Designs," Technical Report No. 87-57, Department of Computer Science, University of Minnesota.
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YEN88a
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H. C. Yen , S. Ghanta , H. C. Du, A path selection algorithm for timing analysis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.720-723, June 12-15, 1988, Atlantic City, New Jersey, United States
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YEN88b
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Yen, H.C. and Du, H.C., "On the General False Path Problem in Timing Analysis," Technical Report No. 88-87, Department of Computer Science, University of Minnesota.
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CITED BY 24
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David Blaauw , Rajendran Panda , Abhijit Das, Removing user specified false paths from timing graphs, Proceedings of the 37th conference on Design automation, p.270-273, June 05-09, 2000, Los Angeles, California, United States
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Li-Ren Liu , David H. C. Du , Hsi-Chuan Chen, An efficient parallel critical path algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.535-540, June 17-22, 1991, San Francisco, California, United States
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M. Ringe , T. Lindenkreuz , E. Barke, Path verification using Boolean satisfiability, Proceedings of the conference on Design, automation and test in Europe, p.965-966, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Hsi-Chuan Chen , David H. C. Du , Li-Ren Liu, Critical path selection for performance optimization, Proceedings of the 28th conference on ACM/IEEE design automation, p.547-550, June 17-22, 1991, San Francisco, California, United States
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Shiang-Tang Huang , Tai Ming Parng , Jyuo Min Shyu, A polynomial-time heuristic approach to approximate a solution to the false path problem, Proceedings of the 30th international conference on Design automation, p.118-122, June 14-18, 1993, Dallas, Texas, United States
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Kurt Keutzer , Sharad Malik , Alexander Saldanha, Is redundancy necessary to reduce delay, Proceedings of the 27th ACM/IEEE conference on Design automation, p.228-234, June 24-27, 1990, Orlando, Florida, United States
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Lei Cheng , Deming Chen , Martin D. F. Wong , Mike Hutton , Jason Govig, Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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