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On the general false path problem in timing analysis
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 555 - 560  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
D. H. Du  Department of Computer Science, University of Minnesota, Minneapolis, MN
S. H. Yen  Department of Computer Science, University of Minnesota, Minneapolis, MN
S. Ghanta  Department of Computer Science, University of Minnesota, Minneapolis, MN
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 13,   Downloads (12 Months): 56,   Citation Count: 24
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ABSTRACT

The false path problem is often referred to as the problem of detecting the longest sensitizable path (A path which is not a false path is a sensitizable path). The term “false path” is not clearly defined. In this paper, we first give a clear and precise definition of a false path. Then the general false path problem is formulated. The general false path problem is to detect whether a given path (not necessarily the longest one) is a false path. We present an efficient algorithm for solving the general false path problem. We also propose another algorithm which generates all the possible sensitizable paths with the delays greater than a given threshold T. The efficiency and effectiveness of the proposed algorithm are demonstrated by the experimental results. Index Terms: Timing Verification, Logic Simulation, VLSI circuit, Timing Analysis, False path, Graph Theory.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
BELL88
Design files provided by ATg~T Bell Labortory.
 
BENK87
Benkowski, J., Vanden Meersch, E., Claesen, L., and De Man, H. "Efficient Algorithms for Solving the False Path Problem in Timing Verification," Proceeding8 of ICCAD-SZ 44-47, 1987.
 
BRAN86
Brand, D. and Iyengar, V. S. "Timing Analysis Using Functional Relal~ionships," Proceeding8 of CCAD-86, 126-129, 1986; (See also "Timing Analysis using Functional Analysis" IBM Research Report, RC 11768(#52821) March 12th ~986.)
 
HITC82a
Hitchcock, R. B., Smith, G. L., and Cheng, D. D. "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, 1, January 1982, 100-105.
 
HITC82b
McWI80
 
OUST85
Ousterhout, J. K. "A Switch-Level Timing Verifier for Digital MOS VLSI," 1EF~E Transaction~ on Computer-Aided Design, Vol. CAD-4, 3, July 1985, 336-349.
 
REDD86
 
ROTH66
J.P. Roth, "Diagnosis of automata failures: A calculus and a new method," IBM J. Res. Develop.,, OCT. 1966, pp. 278-281.
 
SASA81
 
SZYM86
Szymanski, T. G. "LEADOUT: A Static Timing Analyzer for MOS Circuits," Proceeding8 of ICCAD-88, 130-133, 1986.
 
YEN87
Yen, H.C., Ghaaata, S., and Du, H C., "Timing Analysis Algorithms for Large Designs," Technical Report No. 87-57, Department of Computer Science, University of Minnesota.
 
YEN88a
 
YEN88b
Yen, H.C. and Du, H.C., "On the General False Path Problem in Timing Analysis," Technical Report No. 88-87, Department of Computer Science, University of Minnesota.

CITED BY  24

Collaborative Colleagues:
D. H. Du: colleagues
S. H. Yen: colleagues
S. Ghanta: colleagues