A scheme for overlaying concurrent testing of VLSI circuits

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A scheme for overlaying concurrent testing of VLSI circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 531 - 536

Year of Publication: 1989

ISBN:0-89791-310-8

Authors

W.-B. Jone	Department of Computer Science, New Mexico Tech, Socorro, NM
C. A. Papachristou	Department of Computer Engineering and Science, Case Weatem Reserve University, Cleveland, OH
M. Pereira	Department of Computer Science, New Mexico Tech, Socorro, NM

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 9, Citation Count: 4

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a test scheduling method, called overlaying concurrent testing, for built-in testing of VLSI circuits. The scheme is based on a resource-conflict analysis of subcircuits and a scheduling algorithm. The algorithm fully exploits test parallelism by overlaying the test intervals of compatible subcircuits to test as many of them as possible concurrently. The technique is supported by a test hardware architecture whose design is well coordinated with the test scheduling leading to a considerable reduction of testing time, as demonstrated by simulation experiments.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. J. McCluskey, ~Built-in Self-Test Techniques," IEEE DesiCn Test, pp. 21-28, April 1985.
	2	C. R. Kime and K. K. Saluja, "Test scheduling in Testable VLSI Circuits.~ Proc. 1~th Intl. Symposium Fault-Tolerant Computing, 1982, pp. 406-412.
	3	G. L. Craig and C. R. Kime, "Determining Parallel Test Schedules for VLSI Built-in Test,* Department of Electrical and Computer Engineering, Univ. of Wisconsin, Madison, WI. Tech. Rap. ECF_,-84-23, Sap. 1984.
	4	Narsingh Deo, Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation), Prentice-Hall, Inc., Upper Saddle River, NJ, 1974
	5	G. L. Craig , C. R. Kime , K. K. Saluja, Test Scheduling and Control for VLSI Built-in Self-Test, IEEE Transactions on Computers, v.37 n.9, p.1099-1109, September 1988 [doi>10.1109/12.2260]
	6	J. Kalinowski, A. Albicki and J. Beausang, ~Test Control Signal Distribution in Self-Testing VLSI Circuits,~ Prac. IEEE International Conference on Comput,r-Aid~d Des4gn, pp. 60-63, Nov. 1986.

CITED BY 4

	M. Nourani , J. Carletta , C. Papachristou, A scheme for integrated controller-datapath fault testing, Proceedings of the 34th annual conference on Design automation, p.546-551, June 09-13, 1997, Anaheim, California, United States
	Valentin Mureşan , Xiaojun Wang , Valentina Mureşan , Mircea Vlăduţiu, Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints, Journal of Electronic Testing: Theory and Applications, v.20 n.1, p.61-78, February 2004
	Mehrdad Nourani , Joan Carletta , Christos Papachristou, Integrated test of interacting controllers and datapaths, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.401-422, July 2001
	Nicola Nicolici , Bashir M. Al-Hashimi, Efficient BIST hardware insertion with low test application time for synthesized data paths, Proceedings of the conference on Design, automation and test in Europe, p.60-es, January 1999, Munich, Germany