Design for manufacturability and yield

ABSTRACT

This tutorial focuses on the design strategies for VLSI circuits that are aimed at achieving manufacturable, high-yielding chips. We review the current status of statistical design methodologies based upon statistically-valid modeling and process characterization approaches. Both parametric and functional yield maximization strategies are covered. This tutorial argues that by providing a better starting point for manufacturing, the profitability and competitiveness can be significantly improved.

REFERENCES

• 1: W.Maly, AJ. Strojwas and S.W,DLr~tor, "'VL~I Yield Prediction and Estimation: A Unified Framework", IEEE Trans. on CAD, Jan. 1986.
• 2: C,P.Ho,S.E.Hansen and P.M.Fahey, "SUPREM IR-A program for integrated circuit modeling and simulation", Teeh. report, Stanford University, 1984.
• 3: Z.Yu and R.W.Dutton, "SEDAN III-A Generalized Electronic Material Device Analysis Program", Tech. report, Stanford University, 1985.
• 4: S.R.NassiL A.l.Strojwas and S.W.Direetor, "FABRICS II: A Statistically Based IC Fabrication Process Simulator", IEEE Trans. on CAD, Jan. 1984.
• 5: P. If. Mozumder, A. J. Strojwas and D. Bell, "Statistical Process Simulation for CAD/CAM", Proc. of 2988 CICC, lt~.~, May 1988.
• 6: G. E. P. Box, W. G. Hunter, and J. S. Hunter, Statistics for Experimenters: An Introduction to Design. Data Analysis, and Model Building, Wiley, New York, 1978.
• 7: George E P Box , Norman R Draper, Empirical model-building and response surface, John Wiley & Sons, Inc., New York, NY, 1986
• 8: A, R. Alvarez, et aL, "Application of Statistical Design and Response Surface Methods to Computer-Aided VLSI Device Design", 1EEE Trans. on CAD of ICAS, Vol. 7, No. 2, February 1988, pp. 272-288.
• 9: Andrzej Jozef Strojwas, Pattern recognition based methods for ic failure analysis, 1982
• 10: K.K. Low and S.W.D~or, "An Efficient Macromodeling Approach for Statistical IC Process Design", Proc. of lCCAD-88, I~F~, Nov. 1988.
• 11: D. Collins, "'Semiconductor Equipment Modeling Methodology", Master's thesis, Carnegie Mellon, Nov. 1989.
• 12: M.D.Matson and L.A.Glasser, "Macromodeling and OpKmJzation of Digital MOS VLSI Circuits", IEEE Trans. on CAD, Oct. 1986.
• 13: Sani Richard Nassif, A macromodelling approach for simulation of vlsi circuits (computer-aided design), 1986
• 14: j.Benkoski and A.J.Strojwas, "A New Approach to Hierarchical and Statistical Timing Simulations", IEEE Trans. on CAD, Nov. 1987.
• 15: C.H.Stapper, "Modeling of Integrated Circuit Defect Sensitivities", IBM J. Res. Dev., OCt. 1983.
• 16: W.Maly and J. Deszczka, "Yield Estimation Model for VLSI Axcwork Evaluation", Electronic Lener s, Feb. 1983.
• 17: W.Maly, "'Modeling of Lithography Related Yield Losses for CAD of VL,SI Circuits", IEEE Trans. on CAD, Oct. 1985.
• 18: H.Walker and S.W.Director, "'VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits", IEEE Trans. on CAD, Oct. 1986.
• 19: LChen and A.l.Strojwas, "'Realistic Yield Simulation for VLSIC Structural Failures", 1EEE Trans. on CAD, Nov. 1987.
• 20: I. Chen and A.L Strojwas, "Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis", IEEE Trans. on CAD, July 1987.
• 21: C.LB.Spanos and S.W.Director, "Parameter Era.motion for Statistical IC Process Characterization", IEEE Trans. on CAD, Jar,. 1986.
• 22: W. Maly et al., "Double-Bridge Test Structure for the Evaluation of Type, Size and Density of Spot Defects", Tech. report, Carnegie Mellon, July 1987.
• 23: S.R.Nassif, A.J.Strojwas and S.W.Director, "A Method for Worst-Case Analysis of integrated Circuits", IEEE Tram. on CAD, Jan. 1986.
• 24: F. Severson and S. Simpkins, "Hadamard Analysis- An Effective, Systematic Tool for Worst Case Circuit Analysis", Proc. of 1987 CICC, IEEE, May 1987.
• 25: Andrzej J. Strojwas, Statistical Design of Integrated Circuits, IEEE Press, Piscataway, NJ, 1987
• 26: ICSinghaI and LF.Pinel, "'Statistical Design Centering and Tolerancing Using Parametric Sampling", IEEE Trans. on CAS, July 1981.
• 27: S.W.Dis~tor and G.D.Haehtel, "The Simplieial Approximation Approach to Design Centering", IEEE Trans. on CAS, July 1977.
• 28: P.Cox, P.Yang, S.S.Mahant-Shetti, and P. Chatterjee, "Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits", IEEE Trans. on ED, Feb. 1985.
• 29: G.Taguchi and M.S.Phadke, "Quality Engineering through Design Optimization' ', Conf. Records, GLOBECOM84, IEF_~, Nov, 1984.
• 30: M.S.Phadke, et al., "Off-line Qualify Control in integrated Circuit Fabrication Using Experimental Design", The Bell System Tech. J., Nov. 1983.
• 31: R.Razdzn and A.J.Strojwas, "A Statistical Design Rule Developer", 1EEE Trans. on CAD, Oct. 1986.
• 32: W.Moore, W.Maly and A.J.Strojwas (eds.), Yield Modelling and Defect Tolerance in VZ,SI, Adam Hilger, 1987.
• 33: L.R.Carley and W.Maly, "A Circuit Breaker for Redundant IC Systems", Proc. of 2 988 CICC, IUEE, May 1988.
• 34: W. Maly and P.Nigh, "Built-in Current Testing - Feasibility Study"0 Proc. ICCAD-88, IEEE, Nov. 1988.
• 35: R.tCCavin 111 and W.H. Miller, Jr., "Design for Manufacturing", SRC Newsletter, Mar. 1989.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation
  B.m MISCELLANEOUS
      Subjects: Design management

  G. Mathematics of Computing

General Terms:
Algorithms, Design, Experimentation, Management