Differential fault simulation - a fast method using minimal memory

ABSTRACT

A new, fast fault simulator called differential fault simulator, DSIM, for sequential circuits is described. Unlike the concurrent fault simulation, DSIM simulates each machine by simulating its machine differences from the other machine just simulated instead of simulating its input differences from the previous status of the same machine. In this manner, DSIM simulates each machine (good or bad) separately for every test vector. Therefore, DSIM dramatically reduces the dynamic memory requirement and the overhead in the memory management in the concurrent fault simulation. Also unlike the single fault propagation which simulates each bad machine by simulating its machine difference from the good machine, the overhead to restore the good machine status before each bad machine simulation is eliminated in DSIM. Our experiments show that DSIM runs 3-12 times faster than an existing concurrent fault simulator and an experimental single fault propagation simulator. Furthermore, owing to the straightforward operations, DSIM is very easy to implement and maintain. Implementation consists of less than 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential test generation system, STG. Currently DSIM uses a zero-delay timing model, while inclusion of other delay models is under development.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.2 Reliability and Testing**
          Subjects: Test generation**
      B.6.3 Design Aids
          Subjects: Simulation

General Terms:
Algorithms, Design, Verification