Test pattern generation for sequential MOS circuits by symbolic fault simulation

ABSTRACT

The COSMOS symbolic fault simulator generates test sets for combinational and sequential MOS circuits represented at the switch level. All aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values are captured. To generate tests for a circuit, the program derives Boolean functions representing the behavior of the good and faulty circuits over a sequence of symbolic input patterns. It then determines a set of assignments to the input variables that will detect all faults. Symbolic simulation provides a natural framework for the user to supply an overall test strategy, letting the program determine the detailed conditions to detect a set of faults. Symbolic preprocessing of switch-level networks, combined with efficient Boolean manipulation makes this approach feasible.

REFERENCES

• 1: S. B. Akers and B. Krishnamurthy, "On the Application of Test Counting to VLSI Teming," 1985 Chapel Hill Conference on Very Large Scale Integration, Computer Science Press, 1985, pp. 343-360.
• 2: Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
• 3: R. E. Bryant , D. Beatty , K. Brace , K. Cho , T. Sheffler, COSMOS: a compiled simulator for MOS circuits, Proceedings of the 24th ACM/IEEE conference on Design automation, p.9-16, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37890]
• 4: R. E. Bryant. "Boolean Analysis of MOS Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. CAD-6, No. 4 (July, 1987), pp. 634-649.
• 5: H. H. Chen, R. G. Mathews, and J. A. Newkirk, "An Algorithm to Generate Tests for MOS Circuits at the Switch Level," International Test Conference, 1986, pp. 304-312.
• 6: R. I. Damper , N. Burgess, MOS test pattern generation using path algebras, IEEE Transactions on Computers, v.36 n.9, p.1123-1128, Sept. 1987 [doi>10.1109/TC.1987.5009546]
• 7: E Goel. "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, Vol. C-30, No. 3 (March, 1981), pp. 215-222.
• 8: S. K. Jain and V. D. Agrawal. "Modeling and Test Generation Algorithms for MOS Circuits," IEEE Transactions on Co,nputers, Vol. C-34, No. 5 (May, 1985), pp. 426-433.
• 9: Madhukar K. Reddy , Sudhakar M. Reddy , Prathima Agrawal, Transistor level test generation for MOS circuits, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.825-828, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.318007]
• 10: S. H. Robinson and J. P. Shen. "Towards a Switch-Level Test Pattern Generation Program," International Conference on Computer-Aided Design, 1985, pp. 39-41.
• 11: J. Paul Roth, Computer Logic, Testing and Verification, W. H. Freeman & Co., New York, NY, 1980

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits
      B.6.2 Reliability and Testing**
          Subjects: Test generation**
      B.6.3 Design Aids
          Subjects: Simulation

General Terms:
Algorithms, Design, Theory, Verification