Automatic generation of behavioral models from switch-level descriptions

ABSTRACT

This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the structure, regularity, functionality, and control signals in the generation process. New algorithms are proposed and have been implemented for combinational modules and bus structures. A significant speedup has been obtained for these modules of a commercially available chip.

REFERENCES

• 1: D.G. Saab, R. B. Mueller-Thuns, D. T. Blaauw, J. A. Abraham, and J. T. Rahrneh, "CHAMP: Concurrent Hierarchical And Multilevel Program for Simulation of VLSI Circuits," in Proc. IEEE lnt. Conference on Computer-Aided Design, Santa Clara, CA, 1988.
• 2: R. E. Bryant , D. Beatty , K. Brace , K. Cho , T. Sheffler, COSMOS: a compiled simulator for MOS circuits, Proceedings of the 24th ACM/IEEE conference on Design automation, p.9-16, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37890]
• 3: G. Ditlow, W. Donath, and A. Ruehli, "Logic equations for MOSFET circuits," in Proc. of the IEEE International Symposium on Circ~its and Systems, Newport Beach, CA, pp. 752-755, May 1983.
• 4: R.M. Apte, N-S Chang , and J. Abraham, "REDUCE- Logic extraction for NMOS circuits," in IEEE int. Conf. on Circuits and Computers, New York, Oct. 1982.
• 5: I.N. Haij and D.G. Saab, "Symbolic Logic Simulation of MOS Circuits," Proc. International Symposium on Circuits and Systems, pp. 246-249, 1983.
• 6: Z. Barzilai, D. K. Beece, L. M. Huisman, V. S. Iyengar, and G. M. Silberman, "SLS - A Fast Switch-Level Simulator," IEEE Transactions, on CAD, vol. CAD-7, No. 8, pp. 838-849, Aug. 1988.
• 7: A. Brish, R. Keinan, and Y. Ravid, "A Smart System that Compiles RTL Models from ~chematics," VLSI System Design, pp. 32-35, Feb. 1988.
• 8: H.P. Chang and J. A. Abraham, "Llse of High Level Descriptions for Speedup of Fault Siraulation," in Proc. International Test Conference, Washington D.C., pp. 1- 7, Sept. 1987.
• 9: I. Spillinger and G. M. Silberman, "Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine," IEEE Transactions. on CAD, vol. CAD-5, No. 3, pp. 396-404, July 1986.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Simulation
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Verification

General Terms:
Algorithms, Design, Verification