ACM Home Page
Please provide us with feedback. Feedback
IRSIM: an incremental MOS switch-level simulator
Full text PdfPdf (846 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 173 - 178  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
A. Salz  Computer Systems Laboratory, Stanford University, CA
M. Horowitz  Computer Systems Laboratory, Stanford University, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 18,   Citation Count: 28
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/74382.74412
What is a DOI?

ABSTRACT

This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then incrementally resimulated. This allows error correction and circuit operation verification to be performed in time proportional to the size of the modifications rather than the size of the entire circuit. To accomplish this incremental simulation, IRSIM maintains a history of circuit activity during simulation and only resimulates the sections of the circuit that deviate from their history. The program was tested on several corrections to errors that actually occurred in the design of a VLSI microprocessor. These errors were corrected and the circuit was incrementally resimulated 1.6 to 3500 times faster than simulating the entire circuit.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T, Blank. A Survey of Hardware Accelera~rs Used in Computer- Aided Design. IEEE Design and Test of Computers, 1(3):21-39, August 1984.
 
2
 
3
B. Chawla, H.K. (3ummel, and P. Kozah. MOTIS - AMOS Timing Simulator. IEEE Transactions on Circuit:; and Systems, CA5- 22(12):301-310, December 1975.
 
4
 
5
C.-Y. Chu and M. A. Horowitz. Charge-Sharing Models for Switch- Level Simulation. IEEE Transactions on Computer-Aided Design, CAD-6(6): 1053-1061, November 1987.
 
6
M. Horowitz, P. Chow, D. Stark, R.T. Simoni, A. Salz, S. Pr~bylski, J Henncssy, G. Gulak, A. Agarwal, and J.M. Acken. MIPS-X: A 20 MIPS Peak, 32-bit Microprocessor with On-Chip Cache. IEEE Journal of Solid State Circuits, SC-22:790-799, October 1987.
 
7
S.Y. Hwang, T. Blank, and K. Choi. Fast Functional Simulation: An Incremental Approach. IEEE Transactions on Computer-Aided Design, 7(7):765-774, July 1988,
 
8
S.Y. Hwang, T. Blank, and K. Chol. Incremental Functional Simulation of Digital Circuits. In International Conference on Computer- Aided Design, pages 392-395, I~F~E, November 1987.
 
9
ZyCad LE-1001 Product Description. ZYCAD Corporation, 1982.
 
10
Y.H. Lcvendcl. Special-Purpose Computer Logic Simulation using Distributed Processing. B eU System Technical Journal, 6 I(10):2873- 2909, Decernbcr 1982.
 
11
M.R. Lightner, PSI. Moceyunas, H.P. MueIler, B. Vcllandi, and H. Vellandi. CSIM: The Evolution of A Behavioral Level Simulator from a Functional Simulator: Implementation Issues and Performance Measurements. In International Conference on Computer- Aided Design, pages 350-352, IEEE, November 1985.
 
12
Gregory Pfister. The IBM Yorktown Simulation Engine. In Proceedings of the IEEE, pages 850-860, June 1996.
 
13
Christopher J. Terman. Simulation Tools for Digital LSI Design. Phi) thesis, Massachusetts Institute of Technology, October 1983.
 
14
T.E. Williams and M. Horowitz. A Serf-Timed C'3aip for Division. tn Conference on Advanced Research in VLSI, pages 75--96, Stanford University, 1987.

CITED BY  28