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ABSTRACT
This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then incrementally resimulated. This allows error correction and circuit operation verification to be performed in time proportional to the size of the modifications rather than the size of the entire circuit. To accomplish this incremental simulation, IRSIM maintains a history of circuit activity during simulation and only resimulates the sections of the circuit that deviate from their history. The program was tested on several corrections to errors that actually occurred in the design of a VLSI microprocessor. These errors were corrected and the circuit was incrementally resimulated 1.6 to 3500 times faster than simulating the entire circuit.
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Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Riccardo Scarsi, Fast power estimation for deterministic input streams, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.494-501, November 09-13, 1997, San Jose, California, United States
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Alberto Macii , Enrico Macii , Massimo Poncino , Riccardo Scarsi, Stream synthesis for efficient power simulation based on spectral transforms, Proceedings of the 1998 international symposium on Low power electronics and design, p.30-35, August 10-12, 1998, Monterey, California, United States
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Milos Ercegovac , Darko Kirovski , Miodrag Potkonjak, Low-power behavioral synthesis optimization using multiple precision arithmetic, Proceedings of the 36th ACM/IEEE conference on Design automation, p.568-573, June 21-25, 1999, New Orleans, Louisiana, United States
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Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
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Kundan Nepal , Hui-Yuan Song , R. Iris Bahar , Joel Grodstein, RESTA: a robust and extendable symbolic timing analysis tool, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
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