On global wire ordering for macro-cell routing

ABSTRACT

In an automatic routing system for macro-cell layout the wiring area is decomposed into a number of smaller regions. These regions are routed separately by a detailed router such as a channel router or a switch-box router. The position of the pins at the junction between two adjacent regions is usually determined by the detailed router. The locality of this 'bottom-up' ordering disregards the global topologies of the nets which usually span several routing regions. This may result in twisted wires, unnecessary vias and waste of area. An algorithm to prevent twisted wires during detailed routing is presented. A consistent order is determined for the junction pins which ensures that no unnecessary wire twisting is introduced. If wires have to cross their intersection will preferably be placed in such a position that the chip area is least affected.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.2 Input/Output Devices
          Subjects: Data terminals and printers

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design