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Architectural partitioning for system level design
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 62 - 67  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
E. D. Lagnese
D. E. Thomas
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 16
Additional Information:

abstract   cited by   index terms   collaborative colleagues  

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ABSTRACT

Architectural partitioning is introduced as a new phase in system level synthesis. Architectural partitioning extracts high level structure from the behavior of an architecture. This paper describes the APARTY architectural partitioner, an automatic Architectural PARTYtioner that supports synthesis in the System Architect's Workbench. APARTY uses a unique multi-stage clustering technique. Knowledge of the high level structure of an architecture aids synthesis tools in choosing a better design in terms of area. For one example, architectural partitioning reduced the number of wiring tracks in the final design by 20%.


CITED BY  16
Kayhan Kükçakar , Alice C. Parker, CHOP: A constraint-driven system-level partitioner, Proceedings of the 28th conference on ACM/IEEE design automation, p.514-519, June 17-22, 1991, San Francisco, California, United States
Wei Zhao , Christos A. Papachristou, Architectural partitioning of control memory for application specific programmable processors, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.521-526, November 05-09, 1995, San Jose, California, United States
Wing Hang Wong , Rajiv Jain, PARAS: system-level concurrent partitioning and scheduling, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.440-445, November 05-09, 1995, San Jose, California, United States
Miodrag Potkonjak , Wayne Wolf, A methodology and algorithms for the design of hard real-time multitasking ASICs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.430-459, Oct. 1999
Josef Scheichenzuber , Werner Grass , Ulrich Lauther , Sabine März, Global hardware synthesis from behavioral dataflow descriptions, Proceedings of the 27th ACM/IEEE conference on Design automation, p.456-461, June 24-27, 1990, Orlando, Florida, United States
D. S. Rao , F. J. Kurdahi, Partitioning by regularity extraction, Proceedings of the 29th ACM/IEEE conference on Design automation, p.235-238, June 08-12, 1992, Anaheim, California, United States
Rolf Ernst , Jörg Henkel , Thomas Benner, Hardware-software cosynthesis for microcontrollers, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
Giovanni De Micheli , Rajesh K. Gupta, Hardware/software co-design, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
Donald A. Lobo , Barry M. Pangrle, Redundant operator creation: a scheduling optimization technique, Proceedings of the 28th conference on ACM/IEEE design automation, p.775-778, June 17-22, 1991, San Francisco, California, United States
Mehrdad Nourani , Joan Carletta , Christos Papachristou, Integrated test of interacting controllers and datapaths, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.401-422, July 2001
Kyosun Kim , Ramesh Karri , Miodrag Potkonjak, Synthesis of application specific programmable processors, Proceedings of the 34th annual conference on Design automation, p.353-358, June 09-13, 1997, Anaheim, California, United States
Frank Vahid, Procedure cloning: a transformation for improved system-level functional partitioning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.70-96, Jan. 1999
F. Monteiro , B. Rouzeyre , G. Sagnes, High level synthesis: a data path partitioning method dedicated to speed enhancement, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
Victor V. Toporkov, Performance-complexity analysis in hardware-software codesign for real-time systems, Proceedings of the conference on European design automation, p.340-345, September 18-22, 1995, Brighton, England
Miodrag Potkonjak , Wayne Wolf, Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.446-451, November 05-09, 1995, San Jose, California, United States
Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS


General Terms:
Design, Performance

Collaborative Colleagues:
E. D. Lagnese: colleagues
D. E. Thomas: colleagues

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