A scheduling and resource allocation algorithm for hierarchical signal flow graphs

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A scheduling and resource allocation algorithm for hierarchical signal flow graphs

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 7 - 12

Year of Publication: 1989

ISBN:0-89791-310-8

Authors

M. Potkonjack
J. Rabaey

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 8

Additional Information:

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ABSTRACT

The paper describes a new algorithm for the scheduling and resource allocation problem in high-level synthesis. The algorithm can not only efficiently treat flattened signal flow graphs, but also handles graphs with embedded control constructs such as conditional branches and loops. Based on simple and clear, but powerful principles, the algorithm simultaneously minimizes the number of execution units, the number of registers and the amount of interconnections. The algorithm has been implemented and we present the first results, which are very promising.

CITED BY 8

	N. Wehn , H.-J. Herpel , T. Hollstein , P. Poechmueller , M. Glesner, High-level synthesis in a rapid-prototype environment for mechatronic systems, Proceedings of the conference on European design automation, p.188-193, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Nam-Sung Woo, A global, dynamic register allocation and binding for a data path synthesis system, Proceedings of the 27th ACM/IEEE conference on Design automation, p.505-510, June 24-27, 1990, Orlando, Florida, United States
	R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, Proceedings of the conference on Design, automation and test in Europe, p.642-649, March 2001, Munich, Germany
	Han Bin Kim , Dong Sam Ha , Takeshi Takahashi, On ILP formulations for built-in self-testable data path synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.742-747, June 21-25, 1999, New Orleans, Louisiana, United States
	Reiner Hartenstein, Coarse grain reconfigurable architecture (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation, p.564-570, January 2001, Yokohama, Japan
	Ganesh Lakshminarayana , Niraj K. Jha, Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.439-444, June 15-19, 1998, San Francisco, California, United States
	Miodrag Potkonjak , Jan Rabaey, Algorithm selection: a quantitative computation-intensive optimization approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.90-95, November 06-10, 1994, San Jose, California, United States
	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991