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ABSTRACT

This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.

REFERENCES

• Acos 86: R D Acosta , J Kjelstrup , H C Torng, An instruction issuing approach to enhancing performance in multiple functinal unit processors, IEEE Transactions on Computers, v.35 n.9, p.815-828, Sept. 1986 [doi>10.1109/TC.1986.1676841]
• Aho 86: Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
• Apol 88: Apollo Computer Inc. Marketing Brochure. The series 10000 Personal Supercomputer. Chelmsford. MA, 1988.
• Fost 72: C.C. Foster and E.M. Riseman, "Percolation of Code to Enhance Parallel Dispatching and Execution IEEE Transactions on. Computers, Vol. C-21 (December 1972), pp. 1411-1415.
• Henn 86: J.L. Hennessy, "RISC-Based Processors: Concepts and Prospects". New Froniiers in Corn p,ler Architecture Conference Proceedings (hlarch 1986), pp. 95- 103.
• Kell 75: Robert M. Keller, Look-Ahead Processors, ACM Computing Surveys (CSUR), v.7 n.4, p.177-195, Dec. 1975 [doi>10.1145/356654.356657]
• Kuck 72: D.J. Kuck. Y. Muraol,'a, and S. C. hen, "On the Number of Opera. Lions Simultaneously Executable in Fortran-like Programs and Their resulting Speedup". IEEE Transaciions on computers, Vol. C-21 (December 1972), pp. 1293--1310.
• Lee 84: J.K.F. Lee and A.J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design" IEEE Computer (January 1984). pp. 6-22.
• Logr 72: L. Logrippo. "Renamillg in Program Schemas". Proceedings of the IEEE 13th Annual Symposium on switching and Automata Theory. (October 1972), Pp. 67- 70.
• McFa 86: S. McFarling , J. Hennesey, Reducing the cost of branches, Proceedings of the 13th annual international symposium on Computer architecture, p.396-403, June 02-05, 1986, Tokyo, Japan
• MIPS 86: MIPS Computer Systems, Inc., MIPS Language Programmers Guide (1986).
• Nico 84: A. Nicolau and J.A. Fisher, "Mea.suring tile Parallelism Availa.ble for Very Long Instruction Word Architectures". IEEE Transactions on Computers. vol. C-33 (November 1984), pp. 968-976.
• Rise 72: E.hl. Riselnan and C.C. Foster, "The Inhibition of Potential Parallelism by Conditional Pumps". IEEE Transactions on Computers, Vol. C-21 (December 1972), pp. 1405-1411.
• Slav 88: G.A. Slaxenburg, Phillips Research Laboratories Sunnyvale, Signetics Corporation, Sunnyvale, CA. Personal Correspondence, 12 May 1988.
• Smit 87: J. E. Smith , G. E. Dermer , B. D. Vanderwarn , S. D. Klinger , C. M. Rozewski, The ZS-1 central processor, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.199-204, October 1987, Palo Alto, California, United States
• Sohi 87: G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30354]
• Tjad 70: G.S. Tjaden and M.J. Flynn, "Detection and Parallel Execution of Independent. Instructions". IEEE Transacactions on Computers, Vol. C-19 (October 1970), pp. 889-895.
• Toma 67: R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units'. IBM Journal, Vol. 11 (January 1967), pp. 25-33.
• Weis 84: S. Weiss and J.E. Smith, "Instrtlction Issue Logic in Pipelined Supercomputers". IEEE Transaction"s on Computer's, Vol. C-33 (November 1984), pp. 1013-1022.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Experimentation, Measurement, Performance