Two Methods of Rijndael Implementation in Reconfigurable Hardware

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Two Methods of Rijndael Implementation in Reconfigurable Hardware

Source

Lecture Notes In Computer Science; Vol. 2162 archive
Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems table of contents

Pages: 77 - 92

Year of Publication: 2001

ISBN:3-540-42521-7

Authors

Viktor Fischer
Milos Drutarovský

Publisher

Springer-Verlag London, UK

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 13

Additional Information:

cited by collaborative colleagues

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CITED BY 13

	C. Kachris , N. Bourbakis , A. Dollas, A reconfigurable logic-based processor for the SCAN image and video encryption algorithm, International Journal of Parallel Programming, v.31 n.6, p.489-506, December 2003
	François-Xavier Standaert , Gael Rouvroy , Jean-Jacques Quisquater , Jean-Didier Legat, A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Patrick R. Schaumont , Henry Kuo , Ingrid M. Verbauwhede, Unlocking the design secrets of a 2.29 Gb/s Rijndael processor, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Thomas Wollinger , Jorge Guajardo , Christof Paar, Security on FPGAs: State-of-the-art implementations and attacks, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.3, p.534-574, August 2004
	Sumio Morioka , Akashi Satoh, A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.686-691, July 2004
	Stefan Mangard , Manfred Aigner , Sandra Dominikus, A Highly Regular and Scalable AES Hardware Architecture, IEEE Transactions on Computers, v.52 n.4, p.483-491, April 2003
	Xinmiao Zhang , Keshab K. Parhi, High-speed VLSI architectures for the AES algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.957-967, September 2004
	N. Sklavos , O. Koufopavlou, Architectures and VLSI Implementations of the AES-Proposal Rijndael, IEEE Transactions on Computers, v.51 n.12, p.1454-1459, December 2002
	Guido Bertoni , Luca Breveglieri , Israel Koren , Paolo Maistri , Vincenzo Piuri, Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard, IEEE Transactions on Computers, v.52 n.4, p.492-505, April 2003
	Chih-Pin Su , Chia-Lung Horng , Chih-Tsun Huang , Cheng-Wen Wu, A configurable AES processor for enhanced security, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Adam J. Elbirt , Christof Paar, An Instruction-Level Distributed Processor for Symmetric-Key Cryptography, IEEE Transactions on Parallel and Distributed Systems, v.16 n.5, p.468-480, May 2005
	Monjur Alam , Sonai Ray , Debdeep Mukhopadhayay , Santosh Ghosh , Dipanwita RoyChowdhury , Indranil Sengupta, An area optimized reconfigurable encryptor for AES-Rijndael, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Renfei Liu , Keshab K. Parhi, Fast composite field S-box architectures for advanced encryption standard, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA

Collaborative Colleagues:

Viktor Fischer: colleagues

Milos Drutarovský: colleagues

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