1

{Alexander75} W.C. Alexander and D.B. Wortman, "Static and Dynamic characteristics of XPL Programs," Computer, pp. 41--46, November 1975, Vol. 8, No. 11.

2

{Cocke80} J. Cocke, private communication, February, 1980.

3

{Cragon80} H.A. Cragon, in his talk presenting the paper "The Case Against High-Level Language Computers," at the International Workshop on High-Level Language Computer Architecture, May 1980.

4

{Datamation79} Datamation, "IBM Mini a Radical Departure," October 1979, pp. 53--55.

5

David R. Ditzel , David A. Patterson, Retrospective on high-level language computer architecture, Proceedings of the 7th annual symposium on Computer Architecture, p.97-104, May 06-08, 1980, La Baule, United States  [doi>10.1145/800053.801914]

6

{Electronics76} Electronics Magazine, "Altering Computer Architecture is Way to Raise Throughput, Suggests IBM Researchers," December 23, 1976, pp. 30--31.

7

{Foster71} C.C. Foster, R.H. Gonter and E.M. Riseman, "Measures of Op-Code Utilization," IEEE Transactions on Computers, May, 1971, pp. 582--584.

8

{Husson70} S.S. Husson, Microprogramming: Principles and Practices, Prentice-Hall, Engelwood, N.J., pp. 109--112, 1970.

9

{Johnson79} S.C. Johnson, "A 32-bit Processor Design," Computer Science Technical Report # 80, Bell Labs, Murray Hill, New Jersey, April 2, 1979.

10

{Patterson, Séquin80} D.A. Patterson and C.H. Séquin, "Design Considerations for Single-Chip Computers of the Future," IEEE Journal of Solid-State Circuits, IEEE Transactions on Computers, Joint Special Issue on Microprocessors and Microcomputers, Vol. C-29, no. 2, pp. 108--116, February 1980.

11

Bernard L. Peuto , Leonard J. Shustek, An instruction timing model of CPU performance, Proceedings of the 4th annual symposium on Computer architecture, p.165-178, March 23-25, 1977

12

{Shustek78} L.J. Shustek, "Analysis and Performance of Computer Instruction Sets," Stanford Linear Accelerator Center Report 205, Stanford University, May, 1978, pp. 56.

13

{Utley78} B.G. Utley et al, "IBM System/38 Technical Developments," IBM GS80-0237, 1978.

John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983

D. R. Ditzel , H. R. McLellan , A. D. Berenbaum, The hardware architecture of the CRISP microprocessor, Proceedings of the 14th annual international symposium on Computer architecture, p.309-319, June 02-05, 1987, Pittsburgh, Pennsylvania, United States

Keith Diefendorff, History of the PowerPC architecture, Communications of the ACM, v.37 n.6, p.28-33, June 1994

David A. Patterson , Phil Garrison , Mark Hill , Dimitris Lioupis , Chris Nyberg , Tim Sippel , Korbin Van Dyke, Architecture of a VLSI instruction cache for a RISC, ACM SIGARCH Computer Architecture News, v.11 n.3, p.108-116, June 1983

J. A. DeRosa , H. M. Levy, An evaluation of branch architectures, Proceedings of the 14th annual international symposium on Computer architecture, p.10-16, June 02-05, 1987, Pittsburgh, Pennsylvania, United States

David A. Patterson , Carlo H. Sequin, RISC I: A Reduced Instruction Set VLSI Computer, Proceedings of the 8th annual symposium on Computer Architecture, p.443-457, May 12-14, 1981, Minneapolis, Minnesota, United States

Maurice V. Wilkes, Keynote address - the processor instruction set, ACM SIGMICRO Newsletter, v.13 n.4, p.3-5, Dec. 1982

John Hennessy , Norman Jouppi , Forest Baskett , Thomas Gross , John Gill, Hardware/software tradeoffs for increased performance, ACM SIGARCH Computer Architecture News, v.10 n.2, p.2-11, March 1982

David A. Patterson , Carlo H. Sequin, RISC I: a reduced instruction set VLSI computer, 25 years of the international symposia on Computer architecture (selected papers), p.216-230, June 27-July 02, 1998, Barcelona, Spain

J. L. Heath, Re-evaluation of the RISC I, ACM SIGARCH Computer Architecture News, v.12 n.1, p.3-10, March 1984

Thomas E. Anderson , Henry M. Levy , Brian N. Bershad , Edward D. Lazowska, The interaction of architecture and operating system design, ACM SIGPLAN Notices, v.26 n.4, p.108-120, Apr. 1991

Gorden Bell , W. D. Strecker, Retrospective: what have we learned from the PDP-11—what we have learned from VAX and Alpha, 25 years of the international symposia on Computer architecture (selected papers), p.6-10, June 27-July 02, 1998, Barcelona, Spain

David A. Patterson , Richard S. Piepho, RISC assessment: A high-level language experiment, ACM SIGARCH Computer Architecture News, v.10 n.3, p.3-8, April 1982

John L. Hennessy , Thomas R. Gross, Code generation and reorganization in the presence of pipeline constraints, Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.120-127, January 25-27, 1982, Albuquerque, Mexico

David R. Cheriton, An experiment using registers for fast message-based interprocess communication, ACM SIGOPS Operating Systems Review, v.18 n.4, p.12-20, October 1984

Robert P. Colwell , Charles Y. Hitchcock , E. Douglas Jensen, Peering through the RISC/CISC fog: an outline of research, ACM SIGARCH Computer Architecture News, v.11 n.1, p.44-50, March 1983

Brad Burgess , Nasr Ullah , Peter Van Overen , Deene Ogden, The PowerPC 603 microprocessor, Communications of the ACM, v.37 n.6, p.34-42, June 1994

George P. Copeland , Setrag N. Khoshafian, A decomposition storage model, ACM SIGMOD Record, v.14 n.4, p.268-279, May 1985

Daniel T. Fitzpatrick , John K. Foderaro , Manolis G. H. Katevenis , Howard A. Landman , David A. Patterson , James B. Peek , Zvi Peshkess , Carlo H. Séquin , Robert W. Sherburne , Korbin S. Van Dyke, A RISCy approach to VLSI, ACM SIGARCH Computer Architecture News, v.10 n.1, p.28-32, January 1982

Mitch Alsup, Motorola's 88000 Family Architecture, IEEE Micro, v.10 n.3, p.48-66, May 1990

Jack W. Davidson , Richard A. Vaughan, The effect of instruction set complexity on program size and memory performance, ACM SIGPLAN Notices, v.22 n.10, p.60-64, Oct. 1987

Douglas W. Clark , William D. Strecker, Comments on "the case for the reduced instruction set computer," by Patterson and Ditzel, ACM SIGARCH Computer Architecture News, v.8 n.6, p.34-38, October 1980

Beatrice Lazzerini, Effective VLSI Processor Architectures for HLL Computers: The RISC Approach, IEEE Micro, v.9 n.1, p.57-65, January 1989

William C. Hopkins, HLLDA defies RISC: thoughts on RISCs, CISCs, and HLLDAs, ACM SIGMICRO Newsletter, v.14 n.4, December 1983

Michael J. Flynn, Towards better instruction sets, ACM SIGMICRO Newsletter, v.14 n.4, December 1983

Robert I. Winner , Edward M. Carter, Toward type-oriented dynamic vertical migration, ACM SIGMICRO Newsletter, v.14 n.4, December 1983

Keith Adams , Ole Agesen, A comparison of software and hardware techniques for x86 virtualization, ACM SIGOPS Operating Systems Review, v.40 n.5, December 2006

Stephen A. Edwards , Edward A. Lee, The case for the precision timed (PRET) machine, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California

Yunhe Shi , Kevin Casey , M. Anton Ertl , David Gregg, Virtual machine showdown: Stack versus registers, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.4, p.1-36, January 2008

Henry G. Baker, Linear logic and permutation stacks—the Forth shall be first, ACM SIGARCH Computer Architecture News, v.22 n.1, p.34-43, March 1994

David A. Patterson, RISCY patents, ACM SIGARCH Computer Architecture News, v.16 n.4, p.169-191, Sept. 1988

J. W. Davidson , J. V. Gresh, Cint: a RISC interpreter for the C programming language, ACM SIGPLAN Notices, v.22 n.7, p.189-198, July 1987

E. H. Debaere, Instruction-path coprocessing to solve some RISC problems, ACM SIGARCH Computer Architecture News, v.17 n.5, p.83-94, Sep. 1989

Lewis Foti , David English , Richard P. Hopkins , David J. Kinniment , Philip C. Treleaven , Wang Long Wang, Reduced-instruction set multi-microcomputer system, Proceedings of the July 9-12, 1984, national computer conference and exposition, July 09-12, 1984, Las Vegas, Nevada

Ben Lickly , Isaac Liu , Sungjun Kim , Hiren D. Patel , Stephen A. Edwards , Edward A. Lee, Predictable programming on a precision timed architecture, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA

Richard R. Oehler, Reduced instruction set computer (RISC), Encyclopedia of Computer Science, 4th edition, John Wiley and Sons Ltd., Chichester, 2003

David A. Patterson: colleagues

David R. Ditzel: colleagues