1

Jan L. Heath, "A Study of Reduced Instruction Set Computers", M.S. Thesis, EEE Dept., North Dakota State University, 1983

2

R. Grappel, and J. Hemenway, "A tale of four uPs: Benchmarks quantify performance," Electronic Desian News. Vol. 26, No. 7, April I, 1981, pp. 179--265.

3

D. Patterson, and C. Sequin, "A VLSI RISC," IEEE Comuter. Vol. 15, No. 9, September, 1982, pp. 8--18.

4

R. Piepho, "Comparative Evaluation of the RISC I Architecture Via the Computer Family Architecture Benchmarks," Research Project, University of California, Berkeley, August 17, 1981.

5

David A. Patterson , David R. Ditzel, The case for the reduced instruction set computer, ACM SIGARCH Computer Architecture News, v.8 n.6, p.25-33, October 1980  [doi>10.1145/641914.641917]

6

Daniel T. Fitzpatrick , John K. Foderaro , Manolis G. H. Katevenis , Howard A. Landman , David A. Patterson , James B. Peek , Zvi Peshkess , Carlo H. Séquin , Robert W. Sherburne , Korbin S. Van Dyke, A RISCy approach to VLSI, ACM SIGARCH Computer Architecture News, v.10 n.1, p.28-32, January 1982  [doi>10.1145/859520.859524]

7

Robert P. Colwell , Charles Y. Hitchcock , E. Douglas Jensen, Peering through the RISC/CISC fog: an outline of research, ACM SIGARCH Computer Architecture News, v.11 n.1, p.44-50, March 1983  [doi>10.1145/859526.859531]

Philip J. Fleming , John J. Wallace, How not to lie with statistics: the correct way to summarize benchmark results, Communications of the ACM, v.29 n.3, p.218-221, March 1986

Daniel Citron , Adham Hurani , Alaa Gnadrey, The harmonic or geometric mean: does it really matter?, ACM SIGARCH Computer Architecture News, v.34 n.4, p.18-25, September 2006

Humayun Khalid, A trace-driven simulation methodology, ACM SIGARCH Computer Architecture News, v.23 n.5, p.27-33, Dec. 1995