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ABSTRACT
The following computer architecture offers extensible machine language. That is it has an open-ended instruction set. It does this by using the same format for both op-codes and subroutine calls. Theoretically this means that the programmer can chose an instruction set for the application at hand. Ie., the machine language representation of a program can correspond to a high level textual representation or a program.The mechanism of instruction processing for this architecture is essentially a way of encompassing the major categories of interpreters : Direct threaded code, indirect threaded code, and P-code or compressed threaded code. The mechanism is closest in spirit to that of Forth and can be considered a hardware implementation of Forth.Due to the simplicity of instruction set representation, the design is not tied to any one word size. Thus, it is implementable on all the major word sizes (16, 24, 32, 36, 48, 60, or 64 bits).I hope this is perceived as an elegant design.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Moore, C. Aug. 1980. The evolution of FORTH--An unusual language. Byte 5:8:76--92.
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Brakefield, J. May 1982 (tenative). Interpreter mechanism computers. 68 Micro-Journal.
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Brakefield, J. Mar. 1982. DECUS Meeting : FORTH extensions. SIGPLAN NOTICES, pp. 20--21.
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Brakefield, J. Mar. 1981. In the limit. IEEE Computer 14:3:88.
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Brakefield, J. May 1980. A coding discipline for microprocessors. IEEE Computer 13:5:118--119.
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