| Synthesis and placement flow for gain-based programmable regular fabrics |
| Full text |
Pdf
(520 KB)
|
| Source
|
International Symposium on Physical Design
archive
Proceedings of the 2003 international symposium on Physical design
table of contents
Monterey, CA, USA
SESSION: Session 10: Regular Circuit Fabrics (invited)
table of contents
Pages: 197 - 203
Year of Publication: 2003
ISBN:1-58113-650-1
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 6, Downloads (12 Months): 27, Citation Count: 10
|
|
|
ABSTRACT
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gain-based Logic Blocks (GLBs). The GLB is a semi-universal logic block designed based on logical effort theory[12]. Customization of the GLBs is provided by programmable vias. To achieve the best performance, appropriate fabric has to be selected from a family of GLAs with different performance-area trade-offs. We describe a synthesis and placement flow which, for a given design to be implemented, allows us to select the best GLA from the candidate family.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
R. Bryant, K-T. Cheng, A. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey, A. Sangiovanni-Vincentelli, "Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI", Proc. IEEE, vol. 89, issue 3, Mar 2001, pp. 341--365.
|
| |
2
|
|
| |
3
|
J. Cong, Y. Ding, "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13 Issue 1, Jan 1994, pp. 1--12.
|
| |
4
|
H. Dao, V.G. Oklobdzija, "Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders", Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol 2, 2001, pp: 1666--1669.
|
| |
5
|
Joel Grodstein , Eric Lehman , Heather Harkness , Bill Grundmann , Yosinatori Watanabe, A delay model for logic synthesis of continuously-sized networks, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.458-462, November 05-09, 1995, San Jose, California, United States
|
 |
6
|
|
| |
7
|
C.C. Lin, M. Marek-Sadowska, D. Gatlin, "On designing universal logic blocks and their application to FPGA design", IEEE trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, issue 5, May 1997, pp. 519--527.
|
 |
8
|
|
| |
9
|
F. Mo, R.K. Brayton, "Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design", Intl. Workshop on Logic and Synthesis, Jun 2002.
|
 |
10
|
|
| |
11
|
Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
|
| |
12
|
|
| |
13
|
X.Y. Yu, V.G. Oklobdzija, W.W. Walker, "Application of Logical Effort on Design of Arithmetic Blocks", Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol 1, 2001, pp: 872--874
|
CITED BY 10
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Mike Hutton , Richard Yuan , Jay Schleicher , Gregg Baeckler , Sammy Cheung , Kar Keng Chua , Hee Kong Phoo, A methodology for FPGA to structured-ASIC synthesis and verification, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
|
|
|
|
|
|
|
|
|
|
|
|
Po-Yang Hsu , Shu-Ting Lee , Fu-Wei Chen , Yi-Yu Liu, Buffer design and optimization for lut-based structured ASIC design styles, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
|
|