The scaling challenge

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The scaling challenge: can correct-by-construction design help?

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International Symposium on Physical Design archive
Proceedings of the 2003 international symposium on Physical design table of contents

Monterey, CA, USA

SESSION: Session 3: From the Trenches (invited) table of contents

Pages: 51 - 58

Year of Publication: 2003

ISBN:1-58113-650-1

Authors

Prashant Saxena	Intel Labs (CAD Research), Hillsboro, OR
Noel Menezes	Intel Labs (CAD Research), Hillsboro, OR
Pasquale Cocchini	Intel Labs (CAD Research), Hillsboro, OR
Desmond A. Kirkpatrick	Intel Labs (CAD Research), Hillsboro, OR

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 9, Downloads (12 Months): 48, Citation Count: 21

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ABSTRACT

We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correct-by-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

REFERENCES

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