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ABSTRACT

The biggest impact to high-performance microprocessor designs comes from the earliest design planning made up-front in the design. Of these, electrical wire planning is one of the most important. Here, designers begin by understanding the electrical impact of the width and pitch of signals and power rails as well as their inter-relationship. The features of any such pre-set global wire plan will include delay, capacitive and inductive noise, repeater instertion, electromigration, availability of wiring layers, IR drop, allowed design variability, relationship to clock distribution and several other factors. Increasingly, the relationship between each of these factors is becoming more complex and non-obvious. The power delivery network is used not only to deliver power but to shield signals and there is a tradeoff between those two requirements. Signals noise may include low probability inductive noise which is not necessarily useful. When the electrical planning is done, the result will have large implications on routability and design convergence including decap planning. Early physical wiring implication measures should ideally be included with electrical planning, but how will this be done? This talk will focus on the thinking that goes into early wire planning, including signals and power grid, which is usually subsequently fixed for the remainder of the design, and measures which may help to clarify the planning process and its impact will be suggested.