| Prediction of interconnect pattern density distribution: derivation, validation, and applications |
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International Workshop on System-Level Interconnect Prediction
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Proceedings of the 2003 international workshop on System-level interconnect prediction
table of contents
Monterey, CA, USA
SESSION: Session 3: Wirelength Prediction
table of contents
Pages: 85 - 91
Year of Publication: 2003
ISBN:1-58113-627-7
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Downloads (6 Weeks): 2, Downloads (12 Months): 25, Citation Count: 2
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ABSTRACT
A rigorous derivation of the interconnect pattern density distribution for random logic networks is presented using the Bernoulli probability distribution. The derived analytical model provides a statistical interconnect pattern density distribution for a given wiring layer. Sampling window size, average wire length, wiring width and spacing, gate pitch, and wiring utilization are the input parameters.Monte-Carlo simulations agree with the results of the model. Comparison to product data shows that the model also successfully predicts the metal pattern density distribution of actual random logic networks.Several possible applications of the interconnect pattern density prediction are proposed. Among the applications of the model are: quantitative study of interconnect pattern density, statistical interconnect reference circuit for more realistic capacitance estimation, and assessing the impact of metal pattern density variation on system performance.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S. Nassif, "Within-chip variability analysis," Proceedings of IEDM, pp. 283-286, Dec. 1998.
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3
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Vikas Mehrotra , Shiou Lin Sam , Duane Boning , Anantha Chandrakasan , Rakesh Vallishayee , Sani Nassif, A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance, Proceedings of the 37th conference on Design automation, p.172-175, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337370]
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V. Mehrotra, S. Nassif, D. Boning, and J. Chung, "Modeling the effects of manufacturing variations on high-speed microprocessor interconnect performance," Proceedings of IEDM, pp. 767-770, Dec. 1998.
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5
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6
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J. A. Davis, V. K. De and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI): Part I: Derivation and validation," IEEE Transaction on Electron Devices, Vol. 45, No. 3, pp. 580-589, March 1998.
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V. Sukharev, P. Zarkesh-Ha, C.H. Chang, and W. Loh, "Metal density optimization with CMP-based dummy placement," Proceedings of the CMP-MIC Conference, pp. 453-462, February 2003.
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S. Lakshminarayanan, P. Wright, and Jayanthi Pallinti, "Design rule methodology to improve the manufacturability of the copper CMP process," Proceedings of the IEEE IITC, pp. 99-101, June 2002.
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T. Shih, C.H. Yao, L.K. Huang, S.M. Jang, C.H. Yu, and M.S. Liang, "Pattern dependence study of copper planarization using linear polisher for 0.13 mm applications," Proceedings of IEEE IITC, pp. 51-53, June 2001.
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CITED BY 2
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Payman Zarkesh-Ha , Ken Doniger , William Loh , Peter Bendix, Prediction of interconnect adjacency distribution: derivation, validation, and applications, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
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