Switching activity analysis and pre-layout activity prediction for FPGAs

ABSTRACT

It is well-known that dynamic power dissipation in digital CMOS circuits depends linearly on switching activity. In this paper, we study switching activity in a commercial FPGA and propose a novel approach to pre-layout activity prediction. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). Low-power synthesis and early power estimation are typically done on the basis of zero delay activity values, with the assumption that such values correlate well with routed delay activity values. We investigate whether this assumption is valid for FPGA technologies, where critical path delay is often dominated by interconnect delay. We then present an approach for early prediction of routed delay activity values. Our approach is novel in that it estimates each net's routed delay activity using only zero or logic delay activity values along with structural and functional properties of a circuit. Results show that in comparison with zero or logic delay activity values, the predicted activity values are substantially more representative of routed delay activity values.

REFERENCES

• 1: Virtex II Platform FPGA Data Sheet. Xilinx, Inc., San Jose, CA, 2002.
• 2: J. Cong and Y. Ding. Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pages 1--12, January 1994.
• 3: Amir H. Farrahi , Majid Sarrafzadeh, FPGA Technology Mapping for Power Minimization, Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications, p.66-77, September 07-09, 1994
• 4: R. J. Francis, J. Rose, and Z. Vranesic. Technology mapping for lookup table-based FPGAs for performance. In IEEE Int. Conf. on Computer-Aided Design, pages 568--571, 1991.
• 5: Varghese George , Jan M. Rabaey, Low-energy FPGAs: architecture and design, Kluwer Academic Publishers, Norwell, MA, 2001
• 6: Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Timing-driven placement for hierarchical programmable logic devices, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.3-11, February 2001, Monterey, California, United States [doi>10.1145/360276.360286]
• 7: Hao Li , Wai-Kei Mak , Srinivas Katkoori, LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth, Proceedings of the IEEE Computer Society Workshop on VLSI 2001, p.123, April 19-20, 2001
• 8: F. Najm. Transition density: A new measure of activity in digital circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12:310--323, February 1993.
• 9: Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
• 10: Kara K. W. Poon , Andy Yan , Steven J. E. Wilton, A Flexible Power Model for FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.312-321, September 02-04, 2002
• 11: Massoud Pedram , Jan M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, 2002
• 12: Li Shang , Alireza S. Kaviani , Kusuma Bathala, Dynamic power consumption in Virtex™-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503072]
• 13: Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
• 14: Hendrawan Soeleman , Kaushik Roy , Tan-Li Chou, Estimating Circuit Activity in Combinational CMOS Digital Circuits, IEEE Design & Test, v.17 n.2, p.112-119, April 2000 [doi>10.1109/54.844340]
• 15: Gary K. Yeap, Practical low power digital VLSI design, Kluwer Academic Publishers, Norwell, MA, 1998

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Modeling techniques

Keywords:
FPGAs, estimation, field-programmable gate arrays, low-power design, power