Understanding metrics in logic synthesis for routability enhancement

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Understanding metrics in logic synthesis for routability enhancement

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2003 international workshop on System-level interconnect prediction table of contents

Monterey, CA, USA

SESSION: Invited Talk 1 table of contents

Pages: 3 - 5

Year of Publication: 2003

ISBN:1-58113-627-7

Authors

Victor N. Kravets
Prabhakar Kudva	IBM TJ Watson Research Center, Yorktown Heights, NY

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 35, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	BRAYTON, R. K., AND MCMULLEN, C. The decomposition and factorization of Boolean expressions. In Proc. IEEE International Symposium on Circuits and Systems (May 1982), pp. 49--54.
	2	Zhan Chen , Israel Koren, Techniques for Yield Enhancement of VLSI Adders, Proceedings of the IEEE International Conference on Application Specific Array Processors, p.222, July 24-26, 1995
	3	Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France [doi>10.1145/343647.343732]
	4	H. T. Heineken , J. Khare , W. Maly , P. K. Nag , C. Ouyang , W. A. Pleskacz, CAD at the design-manufacturing interface, Proceedings of the 34th annual conference on Design automation, p.321-326, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266123]
	5	Hans T. Heineken , Wojciech Maly, Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.368-373, November 10-14, 1996, San Jose, California, United States
	6	HUIJBREGTS, E. P., XUE, H., AND A. G. JESS. Routing for reliable manufacturing. IEEE Transactions On Semiconductor Manufacturing 8, 2 (Nov. 1995), 188--194.
	7	Israel Koren , Zahava Koren, Incorporating Yield Enhancement into the Floorplanning Process, IEEE Transactions on Computers, v.49 n.6, p.532-541, June 2000 [doi>10.1109/12.862213]
	8	Victor N. Kravets , Karem A. Sakallah, Resynthesis of multi-level circuits under tight constraints using symbolic optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.687-693, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774673]
	9	Prabhakar Kudva , Andrew Sullivan , William Dougherty, Metrics for structural logic synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.551-556, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774653]
	10	W. Maly , H. Heineken , J. Khare , P. K. Nag, Design for manufacturability in submicron domain, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.690-697, November 10-14, 1996, San Jose, California, United States
	11	Rajnish K. Prasad , Israel Koren, The Effect of Placement on Yield for Standard Cell Designs, Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.3-11, October 25-27, 2000
	12	SENTOVICH, E. M. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41, UC Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.
	13	Arunshankar Venkataraman , Israel Koren, Determination of Yield Bounds Prior to Routing, Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.4-13, November 01-03, 1999
	14	YANG, S. Logic synthesis and optimization benchmarks user guide-version 3.0. Microelectronics Center of North Carolina, Research Triangle Park, NC, Jan. 1991.

CITED BY 4

	Qinghua Liu , Malgorzata Marek-Sadowska, Pre-layout wire length and congestion estimation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Qinghua Liu , Malgorzata Marek-Sadowska, Wire length prediction-based technology mapping and fanout optimization, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Robert Lembach , Rafael A. Arce-Nazario , Donald Eisenmenger , Cory Wood, A diagnostic method for detecting and assessing the impact of physical design optimizations on routing, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Robert Fischbach , Jens Lienig , Tilo Meister, From 3D circuit technologies and data structures to interconnect prediction, Proceedings of the 11th international workshop on System level interconnect prediction, July 26-27, 2009, San Francisco, CA, USA