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The Clipper processor: instruction set architecture and implementation
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Communications of the ACM archive
Volume 32 ,  Issue 2  (February 1989) table of contents
Pages: 200 - 219  
Year of Publication: 1989
ISSN:0001-0782
Authors
W. Hollingsworth  Intergraph Corp., Palo Alto, CA
H. Sachs  Intergraph Corp., Palo Alto, CA
A. J. Smith  Univ. of California, Berkeley
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 48,   Citation Count: 7
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ABSTRACT

Intergraph's CLIPPER microprocessor is a high performance, three chip module that implements a new instruction set architecture designed for convenient programmability, broad functionality, and easy future expansion.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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REVIEW

"Trandafir Moisa : Reviewer"

Although most readers are already familiar with the RISC versus CISC debates as one of the most interesting controversies of the last few years, it now seems we have a choice between a RISC, CLIPPER, or CISC architecture. This paper p  more...

Collaborative Colleagues:
W. Hollingsworth: colleagues
H. Sachs: colleagues
A. J. Smith: colleagues