Timing verification and the timing analysis program

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Timing verification and the timing analysis program

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Annual ACM IEEE Design Automation Conference archive
Papers on Twenty-five years of electronic design automation table of contents

Pages: 446 - 456

Year of Publication: 1988

ISBN:0-89791-267-5

Author

R. B. Hitchcock

IBM General Technology Division, Endicott, New York

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 9, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	AG77	B. J. Agule , J. D. Lesser , A. E. Ruehli , P. K. Wolff, An experimental system for power/timing optimization of LSI chips, Proceedings of the 14th conference on Design automation, p.147-152, January 1977
	DO81	W. E. Donath and R. B. Hitchcock, St., "Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks," U. S. Patent No. 4,263,651, April 1981.
	HI82a	R. B. Hitchcock, G. L. Smith, and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, No. I, (pp 100-105), 1982.
	HI82b	R. B. Hitchcock, B. L. Keller, E. Kellerman, J. F. Schroeder, and A. M. Stankosky, "Timing Analysis Results Analyzer", IBM Technical Disclosure Bulletin, Vo1. 24, No. 8, (p 4229), 1982.
	KA81	Ryotaro Kamikawai , Minoru Yamada , Tsuneyo Chiba , Kenichi Furumaya , Yoji Tsuchiya, A critical path delay check system, Proceedings of the 18th conference on Design automation, p.118-123, June 29-July 01, 1981, Nashville, Tennessee, United States
	KI66	T. I. Kirkpatrick and N. R. Clark, "PERT as an Aid to Logic Design," IBM Journal of Research and Development, Vol I0, No. 2, (pp 135-141), March 1966.
	MC78	Thomas M. McWilliams , Lawrence C. Widdoes, Jr., SCALD: Structured Computer-Aided Logic Design, Proceedings of the 15th conference on Design automation, p.271-277, June 19-21, 1978, Las Vegas, Nevada, United States
	MC8O	Thomas M. McWilliams, Verification of timing constraints on large digital systems, Proceedings of the 17th conference on Design automation, p.139-147, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804523]
	PI73	David J. Pilling , Henry B. Sun, Computer-aided prediction of delays in LSI logic systems, Proceedings of the 10th workshop on Design automation, p.182-186, June 25-27, 1973
	RU77	A. E. Ruehli , P. K. Wolff , G. Goertzel, Analytical power/timing optimization technique for digital system, Proceedings of the 14th conference on Design automation, p.142-146, January 1977
	SA81	Tohru Sasaki , Akihiko Yamada , Toshinori Aoyama , Katsutoshi Hasegawa , Shunichi Kato , Shinichi Sato, Hierarchical design verification for large digital systems, Proceedings of the 18th conference on Design automation, p.105-112, June 29-July 01, 1981, Nashville, Tennessee, United States
	WO78	Marvin A. Wold, Design verification and performance analysis, Proceedings of the 15th conference on Design automation, p.264-270, June 19-21, 1978, Las Vegas, Nevada, United States