A linear-time heuristic for improving network partitions

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A linear-time heuristic for improving network partitions

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Annual ACM IEEE Design Automation Conference archive
Papers on Twenty-five years of electronic design automation table of contents

Pages: 241 - 247

Year of Publication: 1988

ISBN:0-89791-267-5

Authors

C. M. Fiduccia	General Electric, Research and Development Center, Schenectady, NY
R. M. Mattheyses	General Electric, Research and Development Center, Schenectady, NY

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 14, Downloads (12 Months): 50, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M A Breuer, "Min-Cut Placement, J. of Design and Fault- Tolerant Computing, Vol. I, number 4, Oct. 1977, pp. 343-362.
	2	Melvin A. Breuer, A class of min-cut placement algorithms, Proceedings of the 14th conference on Design automation, p.284-290, January 1977
	3	B.W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, Vol. 49, Feb. 1970, pp. 291-307.
	4	D. G. Schweikert , B. W. Kernighan, A proper model for the partitioning of electrical circuits, Proceedings of the 9th workshop on Design automation, p.57-62, June 26-28, 1972 [doi>10.1145/800153.804930]
	5	Hiroshi Shiraishi , Fumiyasu Hirose, Efficient placement and routing techniques for master slice LSI, Proceedings of the 17th conference on Design automation, p.458-464, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804570]

CITED BY 14

	Scott Hauck , Gaetano Borriello, Logic partition orderings for multi-FPGA systems, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.32-38, February 12-14, 1995, Monterey, California, United States
	Haifang Liao , Wayne Wei-Ming Dai, Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.704-709, November 05-09, 1995, San Jose, California, United States
	Wen-Jong Fang , Allen C.-H. Wu , Ti-Yen Yen, A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications, Proceedings of the 34th annual conference on Design automation, p.101-106, June 09-13, 1997, Anaheim, California, United States
	Mohammed A. S. Khalid , Jonathan Rose, A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.45-54, February 22-25, 1998, Monterey, California, United States
	Morgan Enos , Scott Hauck , Majid Sarrafzadeh, Replication for logic bipartitioning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.342-349, November 09-13, 1997, San Jose, California, United States
	U. Ober , M. Glesner, Multiway netlist partitioning onto FPGA-based board architecture, Proceedings of the conference on European design automation, p.150-155, September 18-22, 1995, Brighton, England
	Ming-Ter Kuo , Lung-Tien Liu , Chung-Kuan Cheng, Network partitioning into tree hierarchies, Proceedings of the 33rd annual conference on Design automation, p.477-482, June 03-07, 1996, Las Vegas, Nevada, United States
	Tsuyoshi Isshiki , Wayne Wei-Ming Dai, High-level bit-serial datapath synthesis for multi-FPGA systems, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.167-173, February 12-14, 1995, Monterey, California, United States
	Bo Hu , Malgorzata Marek-Sadowska, Fine granularity clustering for large scale placement problems, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Eric S. H. Wong , Evangeline F. Y. Young , W. K. Mak, Clustering based acyclic multi-way partitioning, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
	Kerry Veenstra , Bruce Pedersen , Jay Schleicher , Chiakang Sung, Optimizations for a highly cost-efficient programmable logic architecture, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.20-24, February 22-25, 1998, Monterey, California, United States
	Kunal P. Ganeshpure , Sandip Kundu, Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Kyoung-Hwan Lim , YongHwan Kim , Taewhan Kim, Interconnect and communication synthesis for distributed register-file microarchitecture, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California