A min-cut placement algorithm for general cell assemblies based on a graph representation

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A min-cut placement algorithm for general cell assemblies based on a graph representation

Full text

Pdf (757 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Papers on Twenty-five years of electronic design automation table of contents

Pages: 182 - 191

Year of Publication: 1988

ISBN:0-89791-267-5

Author

U. Lauther

Siemens AG, Munich, FRG

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 24, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/62882.62901 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Konrad W. Koller , Ulrich Lauther, The siemens-avesta-system for computer-aided design of MOS-standard cell circuits, Proceedings of the 14th conference on Design automation, p.153-157, January 1977
	2	G. Persky, D.N. Deutsch, D.G. Schweikert: "LTX-A Minicomputer Based System for Automated LSI Layout", J. Design Aut. & Fault Tol. Comp. Vol. I; Nr. 3, May 1977, pp. 217-256
	3	Th. GUnther: "Die r~umliche Anordnung yon Einheiten mit Wechselbeziehungen", lektronische Datenverarbeitung Nr. 6, 1969, pp. 209-212
	4	Melvin A. Breuer, A class of min-cut placement algorithms, Proceedings of the 14th conference on Design automation, p.284-290, January 1977
	5	M.A. Breuer: "Min-Cut Placement" J. D~sign Aut. & Fault Tol. Comp., Vol. I, Nr. 4 Oct; 1977, pp. 343-362
	6	R.L. Brooks, C.A.B. Smith, A.H. Stone, W.T. Tutte: "The Dissection of Rectangles into Squares" Duke Math. J; 7, ~940, pp. 312-340
	7	0htsuki T; N. Sugiyama, H. Kawanishi: "An Optimization Technique for Integrated Circuit Layout Design", Proc. ICCST-Kyoto, 9/1970, pp. 67-68
	8	Sugiyama N; S. Nemoto, K. Kani, T. 0htsuki, H. Watanabe: "An Integrated Circuit Layout Design Program Based on a Graphtheoretical Approach", IEEE Inter. Solid State Ccts. Conf; Univ. of Pennsylvania, Dig. techn. papers, pp. 86-87, 188 (1979)
	9	K. Zibert: "Ein Beitrag zum rechnergestGtzten topologischen Entwurf yon Hybrid-Schaltungen", Dr. thesis Techn. Univ. Munich, 1974
	10	K. Zibert, R. Saal: "On Cumputer Aided Hybrid Circuit Layout", Proc. 1974 IEEE ISCAS, San Francisco, pp. 314-318
	11	K.D. Brinkmann, D.A. Mlynski: "Computer Aided Chip Minimization for IC-Layout", Proc. 1976 IEEE ISCAS, pp. 650-653
	12	K. Kani, H. Kawanishi, A. Kishimoto: "ROBIN: A Building Block LSI Routing Programm", Proc. 1976 IEEE ISCAS, pp. 658-660
	13	B. T. Preas , C. W. Gwyn, Methods for hierarchical automatic layout of custom LSI circuit masks, Proceedings of the 15th conference on Design automation, p.206-212, June 19-21, 1978, Las Vegas, Nevada, United States
	14	B.W. Kernighan, S. Linn: "An efficient heuristic procedure for partitioning graphs", Bell Syst. Techn. J.; Vol. 49, Feb. 1970, pp. 291-308
	15	D. G. Schweikert , B. W. Kernighan, A proper model for the partitioning of electrical circuits, Proceedings of the 9th workshop on Design automation, p.57-62, June 26-28, 1972 [doi>10.1145/800153.804930]
	16	R. TarJan: "Depth-first search and linear graph algorithms", SIAM J. Comput; Vol. 1, No. 2, June 1972, pp. t46-160