Lazy data routing and greedy scheduling for application-specific signal processors

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Lazy data routing and greedy scheduling for application-specific signal processors

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International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents

San Diego, California, United States

Pages: 111 - 115

Year of Publication: 1988

ISBN:0-8186-1919-8

Authors

K. Rimey	Computer Science Division, University of California, Berkeley, CA
P. N. Hilfinger	Computer Science Division, University of California, Berkeley, CA

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 5, Citation Count: 6

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Joseph A. Fisher , John R. Ellis , John C. Ruttenberg , Alexandru Nicolau, Parallel processing: a smart compiler and a dumb machine, Proceedings of the 1984 SIGPLAN symposium on Compiler construction, p.37-47, June 17-22, 1984, Montreal, Canada
	2	Jan Rabaey, Stephen Pope, and Robert W. Brodersen. An integrated automatic layout generation system for DSP circuits. IEEE Transactions on Computer-Aided Design oflntegrated Circuits, CAD-4(3):285-296, July 1985.
	3	Ken Rimey and Paul N. Nilfinger. A compiler for application-specific signal processors. In The IEEE Workshop on VLSI Signal Processing, November 1988.

CITED BY 6

	William R. Mark , Kekoa Proudfoot, Compiling to a VLIW fragment pipeline, Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, p.47-56, August 2001, Los Angeles, California, United States
	J. L. Linn , C. D. Ardoin, All example of using pseudofields to eliminate version shuffling in horizontal code compaction, ACM SIGMICRO Newsletter, v.20 n.3, p.172-180, Sep. 1989
	Peter Marwedel, Code generation for core processors, Proceedings of the 34th annual conference on Design automation, p.232-237, June 09-13, 1997, Anaheim, California, United States
	Rainer Leupers, Code generation for embedded processors, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Steven Bashford , Rainer Leupers, Constraint driven code selection for fixed-point DSPs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.817-822, June 21-25, 1999, New Orleans, Louisiana, United States
	Qin Zhao , Bart Mesman , Twan Basten, Static resource models for code-size efficient embedded processors, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.219-250, May 2003