Organization of array data for concurrent memory access

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Organization of array data for concurrent memory access

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International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents

San Diego, California, United States

Pages: 97 - 99

Year of Publication: 1988

ISBN:0-8186-1919-8

Authors

M. Breternitz, Jr.	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
J. P. Shen	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 10, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	P. Budnick and D. Kuck. "The Organization and Use of Parallel Memories". IEEETC (Dec. 1971).
	2	W.T.Lin and C.Y.Ho. "A New FFT Mapping Algorithm for Reducing Traffic in a Processor Array". VLSI Signal Processing II (1986).
	3	H. D. Shapiro. "Theoretical Limitations on the Efficient Use of Parallel Memories". ZEEETC (May 1978).
	4	M. Bretemitz Jr and J. P. Shen. "Organization of Array Data for Concurrent Memory Access". CMUCAD 88-39 (Sept. 1988).
	5	Joseph A. Fisher, Very Long Instruction Word architectures and the ELI-512, Proceedings of the 10th annual international symposium on Computer architecture, p.140-150, June 13-17, 1983, Stockholm, Sweden

CITED BY 4

	Mauricio Breternitz, Jr. , John Paul Shen, Architecture synthesis of high-performance application-specific processors, Proceedings of the 27th ACM/IEEE conference on Design automation, p.542-548, June 24-27, 1990, Orlando, Florida, United States
	W. W. Hwu , P. P. Chang, Achieving high instruction cache performance with an optimizing compiler, ACM SIGARCH Computer Architecture News, v.17 n.3, p.242-251, June 1989
	Michael A. Schuette , John P. Shen, An instruction-level performance analysis of the Multiflow TRACE 14/300, Proceedings of the 24th annual international symposium on Microarchitecture, p.2-11, September 1991, Albuquerque, New Mexico, Puerto Rico
	Radoslaw Szymanek , Francky Catthoor , Krzysztof Kuchcinski, Time-Energy Design Space Exploration for Multi-Layer Memory Architectures, Proceedings of the conference on Design, automation and test in Europe, p.10318, February 16-20, 2004