A high-speed hardware unit for a subset of logic resolution

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A high-speed hardware unit for a subset of logic resolution

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International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents

San Diego, California, United States

Pages: 73 - 78

Year of Publication: 1988

ISBN:0-8186-1919-8

Author

D. Wong

Department of Electrical Engineering, Stanford University, Stanford, California

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 6, Citation Count: 0

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ABSTRACT

High-speed engines for logic programming have been the target of much recent research. Here, we present a high-level hardware design and its custom data formats for directly performing a subset of logic resolution. This design uses parallelism in unifying arguments and substituting variable bindings which is distinct from the widely discussed OR and AND parallelism.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Clocksin1	W F. Clocksin , Christopher S. Mellish, Programming in Prolog (2nd ed.), Springer-Verlag New York, Inc., New York, NY, 1984
	Mayr1	E. Mayr and Ullman. 1986, proposed book on parallel processing chapter 2, p. 28.
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	Murakami1	K. Murakami et al. Architectures and Hardware Systems: Parallel Inference Machine and Knowledge Base Machine. Oct. 1984, Technical Report TR-084 from the ICOT Research Center in Tokyo, Japan. ICOT stands for the Institute for New Generation Computer Technology.
	Warren1	D. Warren. An Abstract Prolog Instruction Set. Oct. 1983, Technical Note 309 from the Artificial Intelligence Center, SRI International in Menlo Park, CA.
	Wong1	D. Wong. A High-Speed Hardware Unit for a Subset of Logic Resolution. To be published in 1988 as a Technical Note from the Computer Systems Laboratory at Stanford University.