Mapping of micro data flow computations on parallel microarchitectures

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Mapping of micro data flow computations on parallel microarchitectures

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Source

International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents

San Diego, California, United States

Pages: 70 - 72

Year of Publication: 1988

ISBN:0-8186-1919-8

Authors

L. Shih	Computer Engineering & Science Department, Case Western Reserve University, Cleveland, Ohio
C. A. Papachristou	Computer Engineering & Science Department, Case Western Reserve University, Cleveland, Ohio

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 2

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Andrews80	Michael Andrews, Principles Firmware Engineering, W. H. Freeman & Co., New York, NY, 1980
	Arv82	Arvind, "Data Flow kmguages," lEEE Computer, Special Issue on Data Flow Systems. February 1982.
	Micholsko84	J Mikloško , V E. Kotov, Algorithms, software and hardware of parallel computers, Springer-Verlag, London, 1984
	Stone88	Harold S. Stone, High-performance computer architecture, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1987
	ORAI86	Alex Orailoglu , Daniel D. Gajski, Flow graph representation, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.503-509, July 1986, Las Vegas, Nevada, United States
	Papa88	Papachristou C.. "Partitioning and scheduling of tine grain computations into parallel microarchitectures," Technical Report, CES Dept., CWRU, Jan. 1988.
	STAN81	Stankovic, John A., "The Types and Interactioos of Vertical Migrations of Functions in a Multilevel Interpretive System," iEEE Transactions on Computers, Vol. C-31, No. 7, pp. 505-513, July 1981.

CITED BY 2

	E. S. T. Fernandes, A model for microarchitecture structure evaluation, ACM SIGMICRO Newsletter, v.20 n.3, p.232-236, Sep. 1989
	Liwen Shih, Microprogramming heritage of RISC design, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.275-280, November 27-29, 1990, Orlando, Florida, United States