| Hardware support for large atomic units in dynamically scheduled machines |
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International Symposium on Microarchitecture
archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
table of contents
San Diego, California, United States
Pages: 60 - 63
Year of Publication: 1988
ISBN:0-8186-1919-8
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Authors
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S. W. Melvin
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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M. C. Shebanow
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Y. N. Patt
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 28
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 ABSTRACT
Microarchitectures that implement conventional instruction set architectures are usually limited in that they are only able to execute a small number of microoperations concurrently. This limitation is due in part to the fact that the units of work that the hardware treats as indivisible are small. While this limitation is not important for microarchitectures with a low level of functionality, it can be significant if the goal is to build hardware that can support a large number of microoperations executing concurrently. In this paper we address the tradeoffs associated with the sizes of the various units of work that a processor considers indivisible, or atomic. We argue that by allowing larger units of work to be atomic, restrictions on concurrent operation are reduced and performance is increased. We outline the implementation of a front end for a dynamically scheduled processor with hardware support for large atomic units. We discuss tradeoffs in the design and show that with a modest investment in hardware, the run-time advantages of large atomic units can be realized without the need to alter the instruction set architecture.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Yale N. Patt, Michael C. Shebanow, Wen-mei Hwu and Stephen W. Melvin, "A C Compiler for HPS I. .4 Highly Parallel Execution Engine," Proceedings, 19th Hawaii hternational Conference on System Sciences, Honolulu. HI, January 1986.
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Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow , C. Chen, Run-time generation of HPS microinstructions from a VAX instruction stream, Proceedings of the 19th annual workshop on Microprogramming, p.75-81, October 15-17, 1986, New York, New York, United States
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CITED BY 28
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Eric Rotenberg , Quinn Jacobson , Yiannakis Sazeides , Jim Smith, Trace processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.138-148, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Thomas M. Conte , Sanjeev Banerjia , Sergei Y. Larin , Kishore N. Menezes , Sumedh W. Sathaye, Instruction fetch mechanisms for VLIW architectures with compressed encodings, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.201-211, December 02-04, 1996, Paris, France
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Daniel Holmes Friendly , Sanjay Jeram Patel , Yale N. Patt, Alternative fetch and issue policies for the trace cache fetch mechanism, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.24-33, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Jude A. Rivers , Gary S. Tyson , Edward S. Davidson , Todd M. Austin, On high-bandwidth data cache design for multi-issue processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.46-56, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Oliverio J. Santana , Ayose Falcón , Alex Ramirez , Mateo Valero, Branch predictor guided instruction decoding, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
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