Design of a testable RISC-to-CISC control architecture

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Design of a testable RISC-to-CISC control architecture

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International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents

San Diego, California, United States

Pages: 57 - 59

Year of Publication: 1988

ISBN:0-8186-1919-8

Authors

Y. K. Malaiya	Computer Science Department, Colorado State University, Fort Collins, CO
S. Feng	Computer Science Department, Colorado State University, Fort Collins, CO

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 24, Citation Count: 1

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

A new control architecture is introduced. It is highly testable, and it will support both simple and complex instruction sets. The flexibility is achieved by use of allocable-storage (AS) blocks. An AS block may be assigned to the control part to hold the microcode, or it may be assigned to the data part to hold data or instructions.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. C. Liaw, S. Y. H. Su and Y. K. Malaiya, "State Diagram Approach for Functional Testing of Control Sections," Proc. ITC, Oct. 1981, pp. 433-446.
	2	D. Brahme and J. A. Abraham, "Functional testing of microprocessors," IEEE Trans. Computers, pp.475-485, June 1984.
	3	Y. K. Malaiya, "Option in Control Implementation," Proc. Int. Conf. on Computer Design, 1985, pp. 267-272.
	4	Y. K. Malaiya, "A Testable and Flexible RISC-to-CISC Architecture," 11th Annual IEEE workshop on Design for Testability, April 1988.
	5	V. D. Agrawal, "An Information Theoretic Approach to Digital Fault Testing," IEEE Trans. on Computers, vol. C-30, pp. 582-587, August 1981.
	6	N Mokhoff, New RISC machines appear as hybrids with both RISC and CISC features, Computer Design, v.25 n.7, p.22-25, April 1986
	7	D. Tabak, "Which System is a RISC," Computer, Oct. 1986, pp. 85-86.
	8	Robert P. Colwell , Charles Y. Hitchcock, III , E. D. Jensen , H. M. Brinkley Sprunt , Charles P. Kollar, Computers, complexity, and controversy, Computer, v.18 n.9, p.8-19, Sept. 1985 [doi>10.1109/MC.1985.1663000]
	9	Stanley Habib, Microprogramming and Firmware Engineering Methods, John Wiley & Sons, Inc., New York, NY, 1988
	10	M. Andrews , G. Wey , K. Edwards, Compiler molds microcode to any architecture, Computer Design, v.27 n.9, p.85-88, May 1, 1988
	11	R. A. Mueller, M. R. Duda, P. H. Sweany and J.S. Walicki, "Horizon: A Retargetablo Compiler for Horizontal Micro- Architectures," to be published.
	12	Bipolar Microprocessor Logic and Interface, AMD, 1983, pp. 8.4-8.7.