Power-aware architectures and circuits for FPGA-based signal processing

ABSTRACT

This work showcases a power-aware system design methodology for DSP applications on reconfigurable hardware platforms. In particular, an enhanced FPGA architecture is proposed and analyzed for a deep submicron process technology. These enhancements reduce Configurable Logic Block (CLB) usage for distributed arithmetic implementations of signal processing applications by 50% or more thereby reducing the load on interconnect resources. Multi-Threshold CMOS (MTCMOS) circuit design techniques are aggressively applied to reduce subthreshold leakage using an auto power-down feature for unused logic. Results show a 14x reduction in leakage current for unused CLBs or CLBs in deep sleep mode. CLBs in active mode see up to 2.8x steady-state power reduction. A testchip demonstrating these techniques in 0.13 micron technology has been sent out for fabrication.