Architecture evaluation for power-efficient FPGAs

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Architecture evaluation for power-efficient FPGAs

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays table of contents

Monterey, California, USA

SESSION: Architecture analysis and automation table of contents

Pages: 175 - 184

Year of Publication: 2003

ISBN:1-58113-651-X

Authors

Fei Li	University of California, Los Angeles, CA
Deming Chen	University of California, Los Angeles, CA
Lei He	University of California, Los Angeles, CA
Jason Cong	University of California, Los Angeles, CA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 21, Downloads (12 Months): 137, Citation Count: 38

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the framework fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤: 0.10um technology).

REFERENCES

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CITED BY 38

	Deming Chen , Jason Cong , Yiping Fan, Low-power high-level synthesis for FPGA architectures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Yan Lin , Fei Li , Lei He, Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Fei Li , Yan Lin , Lei He, FPGA power reduction using configurable dual-Vdd, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Arifur Rahman , Vijay Polavarapuv, Evaluation of low-leakage design techniques for field programmable gate arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Deming Chen , Jason Cong, Register binding and port assignment for multiplexer optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.68-73, January 27-30, 2004, Yokohama, Japan
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Kara K. W. Poon , Steven J. E. Wilton , Andy Yan, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.279-302, April 2005
	Andrea Lodi , Luca Ciccarelli , Roberto Giansante, Combining low-leakage techniques for FPGA routing design, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	A. Gayasen , Y. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , T. Tuan, Reducing leakage energy in FPGAs using region-constrained placement, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Yan Lin , Fei Li , Lei He, Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Yan Lin , Lei He, Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Somsubhra Mondal , Seda Ogrenci Memik, Fine-grain leakage optimization in SRAM based FPGAs, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal module and voltage assignment for low-power, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Vijay Degalahal , Tim Tuan, Methodology for high level estimation of FPGA power consumption, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Lerong Cheng , Phoebe Wong , Fei Li , Yan Lin , Lei He, Device and architecture co-optimization for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Mingjie Lin , Abbas El Gamal , Yi-Chang Lu , Simon Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Rajarshee P. Bharadwaj , Rajan Konar , Poras T. Balsara , Dinesh Bhatia, Exploiting temporal idleness to reduce leakage power in programmable architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Julien Lamoureux , Steven J. E. Wilton, FPGA clock network architecture: flexibility vs. area and power, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Suresh Srinivasan , A. Gayasen , N. Vijaykrishnan , T. Tuan, Leakage control in FPGA routing fabric, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yan Lin , Yu Hu , Lei He , Vijay Raghunat, An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006
	Akhilesh Kumar , Mohab Anis, An analytical state dependent leakage power model for FPGAs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Mingjie Lin , Abbas El Gamal, A routing fabric for monolithically stacked 3D-FPGA, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	Chi-Feng Li , Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang, Post-placement leakage optimization for partially dynamically reconfigurable FPGAs, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Lei Cheng , Deming Chen , Martin D. F. Wong, GlitchMap: an FPGA technology mapper for low power considering glitches, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004
	J. H. Anderson , F. N. Najm, Low-power programmable routing circuitry for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.602-609, November 07-11, 2004
	Ho-Yan Wong , Lerong Cheng , Yan Lin , Lei He, FPGA device and architecture evaluation considering process variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.19-24, November 06-10, 2005, San Jose, CA
	Akhilesh Kumar , Mohab Anis, Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance, Proceedings of the 7th International Symposium on Quality Electronic Design, p.735-740, March 27-29, 2006
	Cheng-Tao Hsieh , Jason Cong , Zhiru Zhang , Shih-Chieh Chang, Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Tomasz S. Czajkowski , Stephen D. Brown, Using negative edge triggered ffs to reduce glitching power in FPGA circuits, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Julien Lamoureux , Steven J. E. Wilton, On the trade-off between power and flexibility of FPGA clock networks, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.3, p.1-33, September 2008
	Jason Cong , Junjuan Xu, Simultaneous FU and register binding based on network flow method, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Qiang Wang , Subodh Gupta , Jason H. Anderson, Clock power reduction for virtex-5 FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
	Quang Dinh , Deming Chen , Martin D.F. Wong, A routing approach to reduce glitches in low power FPGAs, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
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