Using logic duplication to improve performance in FPGAs

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Using logic duplication to improve performance in FPGAs

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays table of contents

Monterey, California, USA

SESSION: Logic synthesis and mapping table of contents

Pages: 136 - 142

Year of Publication: 2003

ISBN:1-58113-651-X

Authors

Karl Schabas	University of Toronto, Toronto, Canada
Stephen D. Brown	University of Toronto, Toronto, Canada

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 22, Citation Count: 8

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ABSTRACT

The purpose of this paper is to introduce a modified packing and placement algorithm for FPGAs that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative FPGA architecture using .18 mm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 8

	Peter Suaris , Lungtien Liu , Yuzheng Ding , Nanchi Chou, Incremental physical resynthesis for timing optimization, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Mike Hutton , David Karchmer , Bryan Archell , Jason Govig, Efficient static timing analysis and applications using edge masks, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Tomasz S. Czajkowski , Jonathan Rose, A synthesis oriented omniscient manual editor, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Hosung (Leo) Kim , John Lillis , Miloš Hrkić , Miloš Hrkić, Techniques for improved placement-coupled logic replication, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Hosung (Leo) Kim , John Lillis, A framework for layout-level logic restructuring, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Taneem Ahmed , Paul D. Kundarewich , Jason H. Anderson , Brad L. Taylor , Rajat Aggarwal, Architecture-specific packing for virtex-5 FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Julien Lamoureux , Steven J. E. Wilton, On the trade-off between power and flexibility of FPGA clock networks, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.3, p.1-33, September 2008
	Val Pevzner , Andrew Kennings , Andy Fox, Physical optimization for FPGAs using post-placement topology rewriting, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA