On the properties of the input pattern fault model

ABSTRACT

A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

REFERENCES

• 1: Miron Abramovici, DOs and DON'Ts in Computing Fault Coverage, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.594, October 17-21, 1993
• 2: Abramovici, M., Breuer, M. A., and Friedman, A. D. 1990. Digital Systems Testing and Testable Design. Computer Science Press, New York, NY.
• 3: R. D. Blanton , J. P. Hayes, Design of a fast, easily testable ALU, Proceedings of the 14th IEEE VLSI Test Symposium (VTS '96), p.9, April 28-May 01, 1996
• 4: R. D. Blaton , John P. Hayes, Testability of Convergent Tree Circuits, IEEE Transactions on Computers, v.45 n.8, p.950-963, August 1996 [doi>10.1109/12.536237]
• 5: Brglez, F. and Fujiwara, H. 1985. A neutral netlist of 10 combinational benchmark circuits and a target simulator in Fortran. In Proceedings of the 1985 International Symposium on Circuits and Systems 695--698.
• 6: Brian Chess , Tracy Larrabee, Bridge fault simulation strategies for CMOS integrated circuits, Proceedings of the 30th international conference on Design automation, p.458-462, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164976]
• 7: Chess, B. and Larrabee, T. 1994. Generating test patterns for bridge faults in CMOS ICs. In Proceedings of the European Test Conference (1994).
• 8: Ferguson, F. J. and Shen, J. P. 1985. Inductive fault analysis of MOS integrated circuits. IEEE Des. Test Comput. 2, 6 (Dec.), 13--26.
• 9: Galiay, J., Crouzet, Y., and Vergniault, M. 1980. Physical versus logical fault models of MOS LSI circuits: Impact on their testability. IEEE Trans. Comput. C-29, 6 (June), 527--531.
• 10: Hayes, J. P. 1985. Fault modeling. IEEE Des. Test Comput. 2, 2 (April), 88--95.
• 11: John P. Hayes, Introduction to Digital Logic Design, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1993
• 12: Kautz, W. H. 1967. Testing for faults in cellular logic arrays. In Proceedings of the 8th Symposium on Switching Automata Theory. 161--174.
• 13: J. Khare , W. Maly , N. Tiday, Fault characterization of standard cell libraries using inductive contamination, Proceedings of the 14th IEEE VLSI Test Symposium (VTS '96), p.405, April 28-May 01, 1996
• 14: Larrabee, T. 1989. Efficient generation of test patterns using Boolean Difference. In Proceedings of the International Test Conference (Oct.). 795--801.
• 15: Hyung Ki Lee , Dong Sam Ha, SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits, Proceedings of the 27th ACM/IEEE conference on Design automation, p.660-666, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123432]
• 16: Hyung Ki Lee , Dong Sam Ha, An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.946-955, October 26-30, 1991
• 17: Lee, H. K. and Ha, D. S. 1993. On the generation of test patterns for combinational circuits. Technical Report 12_93, Department of Electrical Engineering Virginia Polytechnic Institute and State University, Blacksburg, VA.
• 18: Thomas Lynch , Earl E. Swartzlander, Jr., A Spanning Tree Carry Lookahead Adder, IEEE Transactions on Computers, v.41 n.8, p.931-939, August 1992 [doi>10.1109/12.156535]
• 19: W. Maly, Realistic fault modeling for VLSI testing, Proceedings of the 24th ACM/IEEE conference on Design automation, p.173-180, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37914]
• 20: S. Muroga , Y. Kambayashi , H. C. Lai , J. N. Culliney, The Transduction Method-Design of Logic Networks Based on Permissible Functions, IEEE Transactions on Computers, v.38 n.10, p.1404-1424, October 1989 [doi>10.1109/12.35836]
• 21: Pomeranz, I. and Reddy, S. M. 1998. Test sequences to achieve high defect coverage for synchronous sequential circuits. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 17, 10 (Oct.), 1017--1029.
• 22: Reddy, S. M., Pomeranz, I., and Kahihara, S. 1998. Compact test sets for high defect coverage. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 16, 8 (Aug.), 923--930.
• 23: Watanabe, Y., Guerra, L. M., and Brayton, R. K. 1996. Permissible functions for multi-output components in combinational logic optimization. IEEE Trans. Comput.-Aided Des. C-15, 7 (July), 732--744.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Design, Performance, Reliability, Verification

Keywords:
ATPG, defects, fault models, fault testing, faults, testing digital circuits