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A stateless, content-directed data prefetching mechanism
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Source Architectural Support for Programming Languages and Operating Systems archive
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems table of contents
San Jose, California
SESSION: Coordinating memory table of contents
Pages: 279 - 290  
Year of Publication: 2002
ISBN:1-58113-574-2
Also published in ...
Authors
Robert Cooksey  Intel Corporation
Stephan Jourdan  Intel Corporation
Dirk Grunwald  University of Colorado
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGOPS: ACM Special Interest Group on Operating Systems
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 14,   Downloads (12 Months): 150,   Citation Count: 28
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ABSTRACT

Although central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. Recently, several proposals have posited a memory-side prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. Alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch likely misses.This paper proposes Content-Directed Data Prefetching, a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. This technique is modeled after conservative garbage collection, and prefetches "likely" virtual addresses observed in memory references. This prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using no additional processor state. By adding less than ½% space overhead to the second level cache, performance can be further increased to 12.6% across a range of "real world" applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H.-J. Boehm. Hardware and operating system support for conservative garbage collection. In International Workshop on Memory Management, pages 61-67, Palo Alto, California, October 1991. IEEE Press.
 
2
M. Charney and A. Reeves. Generalized correlation based hardware prefetching. Technical Report EE-CEG-95-1, Cornell University, February 1995.
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CITED BY  28
Collaborative Colleagues:
Robert Cooksey: colleagues
Stephan Jourdan: colleagues
Dirk Grunwald: colleagues