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Bytecode fetch optimization for a Java interpreter
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Source Architectural Support for Programming Languages and Operating Systems archive
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems table of contents
San Jose, California
SESSION: System performance and optimization table of contents
Pages: 58 - 67  
Year of Publication: 2002
ISBN:1-58113-574-2
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Authors
Kazunori Ogata  IBM Tokyo Research Laboratory, Yamato-shi, Kanagawa, Japan
Hideaki Komatsu  IBM Tokyo Research Laboratory, Yamato-shi, Kanagawa, Japan
Toshio Nakatani  IBM Tokyo Research Laboratory, Yamato-shi, Kanagawa, Japan
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGOPS: ACM Special Interest Group on Operating Systems
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

Interpreters play an important role in many languages, and their performance is critical particularly for the popular language Java. The performance of the interpreter is important even for high-performance virtual machines that employ just-in-time compiler technology, because there are advantages in delaying the start of compilation and in reducing the number of the target methods to be compiled. Many techniques have been proposed to improve the performance of various interpreters, but none of them has fully addressed the issues of minimizing redundant memory accesses and the overhead of indirect branches inherent to interpreters running on superscalar processors. These issues are especially serious for Java because each bytecode is typically one or a few bytes long and the execution routine for each bytecode is also short due to the low-level, stack-based semantics of Java bytecode. In this paper, we describe three novel techniques of our Java bytecode interpreter, write-through top-of-stack caching (WT), position-based handler customization (PHC), and position-based speculative decoding (PSD), which ameliorate these problems for the PowerPC processors. We show how each technique contributes to improving the overall performance of the interpreter for major Java benchmark programs on an IBM POWER3 processor. Among three, PHC is the most effective one. We also show that the main source of memory accesses is due to bytecode fetches and that PHC successfully eliminates the majority of them, while it keeps the instruction cache miss ratios small.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Kazunori Ogata: colleagues
Hideaki Komatsu: colleagues
Toshio Nakatani: colleagues