An efficient technique for exploring register file size in ASIP synthesis

ABSTRACT

Performance estimation is a crucial operation which drives the design space exploration in Application Specific Instruction Set Processors (ASIP) synthesis. The usual approach to estimate performance is to do simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. This problem can be solved by scheduler based approaches, which are much faster. However existing scheduler based approaches do not help in exploring storage organization. This paper presents a scheduler based technique for exploring register file size in ASIP synthesis.The performance is estimated by estimating the number of spills for a particular register file size. The concept of register reuse chains is used for local register allocation. Live variable analysis is done across all the blocks to estimate global register needs. The technique is fast, accurate and retargetable and does not require code generation.Performance estimates for register file sizes between 1 to 8 for ARM (ARM7TDMI) and 1 to 128 for Trimedia (TM-1000) were generated for selected benchmarks to validate the proposed technique. Results show that our estimates are within 9.6% for ARM7T- DMI and 3.3% for TM-1000 compared to the actual performance produced by standard tool sets. Further, this technique is nearly 77 times faster compared to the simulator based technique encc.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
ASIP Synthesis, design space exploration, global analysis, instruction scheduling, liveness analysis, register file, register spill, retargetable estimation, storage exploration