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A case for dynamic pipeline scaling
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Grenoble, France
SESSION: Session 2: embedded system techniques (1) table of contents
Pages: 1 - 8  
Year of Publication: 2002
ISBN:1-58113-575-0
Authors
Jinson Koppanalil  North Carolina State University, Raleigh, NC
Prakash Ramrakhyani  North Carolina State University, Raleigh, NC
Sameer Desai  North Carolina State University, Raleigh, NC
Anu Vaidyanathan  North Carolina State University, Raleigh, NC
Eric Rotenberg  North Carolina State University, Raleigh, NC
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Energy consumption can be reduced by scaling down frequency when peak performance is not needed. A lower frequency permits slower circuits, and hence a lower supply voltage. Energy reduc¿tion comes from voltage reduction, a technique called Dynamic Voltage Scaling (DVS).This paper makes the case that the useful frequency range of DVS is limited because there is a lower bound on voltage. Lowering fre¿quency permits voltage reduction until the lowest voltage is reached. Beyond that point, lowering frequency further does not save energy because voltage is constant.However, there is still opportunity for energy reduction outside the influence of DVS. If frequency is lowered enough, pairs of pipe¿line stages can be merged to form a shallower pipeline. The shal¿low pipeline has better instructions-per-cycle (IPC) than the deep pipeline. Since energy also depends on IPC, energy is reduced for a given frequency. Accordingly, we propose Dynamic Pipeline Scaling (DPS). A DPS-enabled deep pipeline can merge adjacent pairs of stages by making the intermediate latches transparent and disabling corresponding feedback paths. Thus, a DPS-enabled pipeline has a deep mode for higher frequencies within the influ¿ence of DVS, and a shallow mode for lower frequencies. Shallow mode extends the frequency range for which energy reduction is possible. For frequencies outside the influence of DVS, a DPS-enabled deep pipeline consumes from 23% to 40% less energy than a rigid deep pipeline.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Alpha 21264 Microprocessor Hardware Reference Manual http://ftp.digital.com/pub/Digital/info/semiconductor/literature/21264hrm.pdf
4
5
 
6
 
7
K.Bult. Analog Design in Deep Sub-Micron CMOS. 26th European Solid State Circuits Conference, Sep. 2000.
 
8
 
9
D. Burger, T. M. Austin, and S. Bennet. Evaluating Future Microprocessors: The Simplescalar Tool Set. Tech. Rep. CS-TR-96-1308, Univ. Of Wisc.-Madison, July 1996.
 
10
11
 
12
Crusoe™ Processor Model TM5800 Product Brief http://www.transmeta.com/pdf/specifications/ productbrief_tm5800_05jul01.pdf
 
13
Crusoe™ Processor Model TM5400 Product Brief http://www.transmeta.com/technology/specifications/tm5400.html
 
14
J. L. Gonzalez, X. Aragones, F. Moll, and A. Rubio. Scaling Trends for Delta Noise in Sub-Micron CMOS Technologies. Design of Integrated Circuits and Systems, Sevilla, Spain, Nov.1996.
 
15
J. L. Gonzalez and A. Rubio. Delta-I Noise Scaling in Sub-Micron CMOS Technologies. Workshop on Signal Propagation on Interconnects, Travemunde, Germany, May 1997.
16
 
17
D. Grunwald, P. Levis, C Morrey III, M. Neufeld, and K. Farkas. Policies for Dynamic Clock Scheduling. Symp. on Operating Systems Design and Implementation, Oct. 2000.
 
18
R. Ho, K. W. Mai, and M. A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490--504, April 2001.
19
20
21
 
22
23
24
 
25
S. McFarling. Combining Branch Predictors. Technical Report WRL-TN-36, Compaq-WRL, June 1993.
 
26
T. Pering, T. Burd, and R. Brodersen. The Simulation of Dynamic Voltage Scaling Algorithms. Symposium on Low Power Electronics, Oct. 2000.
 
27
M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for Reduced CPU Energy. 1st Symp. on Operating Systems Design and Implementation, Nov. 1994.


Collaborative Colleagues:
Jinson Koppanalil: colleagues
Prakash Ramrakhyani: colleagues
Sameer Desai: colleagues
Anu Vaidyanathan: colleagues
Eric Rotenberg: colleagues