| A case for dynamic pipeline scaling |
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems
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Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
table of contents
Grenoble, France
SESSION: Session 2: embedded system techniques (1)
table of contents
Pages: 1 - 8
Year of Publication: 2002
ISBN:1-58113-575-0
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Authors
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Jinson Koppanalil
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North Carolina State University, Raleigh, NC
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Prakash Ramrakhyani
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North Carolina State University, Raleigh, NC
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Sameer Desai
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North Carolina State University, Raleigh, NC
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Anu Vaidyanathan
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North Carolina State University, Raleigh, NC
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Eric Rotenberg
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North Carolina State University, Raleigh, NC
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Downloads (6 Weeks): 1, Downloads (12 Months): 45, Citation Count: 7
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ABSTRACT
Energy consumption can be reduced by scaling down frequency when peak performance is not needed. A lower frequency permits slower circuits, and hence a lower supply voltage. Energy reduc¿tion comes from voltage reduction, a technique called Dynamic Voltage Scaling (DVS).This paper makes the case that the useful frequency range of DVS is limited because there is a lower bound on voltage. Lowering fre¿quency permits voltage reduction until the lowest voltage is reached. Beyond that point, lowering frequency further does not save energy because voltage is constant.However, there is still opportunity for energy reduction outside the influence of DVS. If frequency is lowered enough, pairs of pipe¿line stages can be merged to form a shallower pipeline. The shal¿low pipeline has better instructions-per-cycle (IPC) than the deep pipeline. Since energy also depends on IPC, energy is reduced for a given frequency. Accordingly, we propose Dynamic Pipeline Scaling (DPS). A DPS-enabled deep pipeline can merge adjacent pairs of stages by making the intermediate latches transparent and disabling corresponding feedback paths. Thus, a DPS-enabled pipeline has a deep mode for higher frequencies within the influ¿ence of DVS, and a shallow mode for lower frequencies. Shallow mode extends the frequency range for which energy reduction is possible. For frequencies outside the influence of DVS, a DPS-enabled deep pipeline consumes from 23% to 40% less energy than a rigid deep pipeline.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 7
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Serkan Ozdemir , Arindam Mallik , Ja Chun Ku , Gokhan Memik , Yehea Ismail, Variable latency caches for nanoscale processor, Proceedings of the 2007 ACM/IEEE conference on Supercomputing, November 10-16, 2007, Reno, Nevada
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