Low-power data memory communication for application-specific embedded processors

ABSTRACT

We propose a novel customization methodology for power reduction on the communication link between an embedded processor and its data memory. We target the address bus and show how by utilizing application information about the memory references in the data intensive program loops, a power efficient address communication protocol can be established between the processor core and the data memory. The data memory controller thus generates the addresses for the various data streams with minimal run-time information from the processor engine, achieving significant power reductions on the address bus. An efficient reprogrammable hardware support is presented for enabling the proposed methodology. The experimental results demonstrate the efficacy of the approach for a set of data intensive applications.

REFERENCES

• 1: P. Petrov and A. Orailoglu, "Performance and power effectiveness in embedded processors - Customizable Partitioned Caches", IEEE TCAD, vol. 20, n. 11, pp. 1309--1318, November 2001.
• 2: Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.212-221, June 1999 [doi>10.1109/92.766748]
• 3: Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
• 4: Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
• 5: Nikolaos Bellas , Ibrahim Hajj , Constantine Polychronopoulos, Using dynamic cache management techniques to reduce energy in a high-performance processor, Proceedings of the 1999 international symposium on Low power electronics and design, p.64-69, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313856]
• 6: Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
• 7: Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
• 8: Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram, Irredundant address bus encoding for low power, Proceedings of the 2001 international symposium on Low power electronics and design, p.182-187, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383128]
• 9: Mahesh Mamidipaka , Dan Hirschberg , Nikil Dutt, Low power address encoding using self-organizing lists, Proceedings of the 2001 international symposium on Low power electronics and design, p.188-193, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383129]
• 10: Monica D. Lam , Edward E. Rothberg , Michael E. Wolf, The cache performance and optimizations of blocked algorithms, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.63-74, April 08-11, 1991, Santa Clara, California, United States
• 11: Michael E. Wolf , Monica S. Lam, A data locality optimizing algorithm, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.30-44, June 24-28, 1991, Toronto, Ontario, Canada
• 12: Joyce Nakamura, Applied Numerical Methods with Software, Prentice Hall PTR, Upper Saddle River, NJ, 1990
• 13: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS

General Terms:
Algorithms, Design, Experimentation, Performance