| Data memory design considering effective bitwidth for low-energy embedded systems |
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International Symposium on Systems Synthesis
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Proceedings of the 15th international symposium on System Synthesis
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Kyoto, Japan
SESSION: Low power memory system
table of contents
Pages: 201 - 206
Year of Publication: 2002
ISBN:1-58113-576-9
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Authors
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Yun Cao
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Kyushu University, Fukuoka 816-8580, Japan
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Hiroyuki Tomiyama
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Institute of Systems & Information Technologies, Momochihama, Fukuoka 814-0001, Japan
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Takanori Okuma
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Kyushu University, Fukuoka 816-8580, Japan
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Hiroto Yasuura
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Kyushu University, Fukuoka 816-8580, Japan
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Downloads (6 Weeks): 5, Downloads (12 Months): 30, Citation Count: 9
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ABSTRACT
This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for application-specific systems, called VAbM technique. It targets the exploitation of both data locality and effective bitwidth of variables to reduce energy consumed by redundant bits. Under constraints of the number of memory banks, the VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple memory banks, which have different size with different number of word lines and different number of bit lines tailored to each application requirements. Experimental results with several real embedded applications demonstrate significant energy reduction up to 64.8% over monolithic memory, and 18.4% over memory designed by banking technique.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 9
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O. Ozturk , M. Kandemir , G. Chen , M. J. Irwin , M. Karakoy, Customized on-chip memories for embedded chip multiprocessors, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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W. Zhang , J. S. Hu , V. Degalahal , M. Kandemir , N. Vijaykrishnan , M. J. Irwin, Reducing instruction cache energy consumption using a compiler-based strategy, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.1, p.3-33, March 2004
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M. Kandemir , O. Ozturk , M. Karakoy, Dynamic on-chip memory management for chip multiprocessors, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
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Russell Tessier , Vaughn Betz , David Neto , Thiagaraja Gopalsamy, Power-aware RAM mapping for FPGA embedded memory blocks, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
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