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A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units
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Source International Symposium on Systems Synthesis archive
Proceedings of the 15th international symposium on System Synthesis table of contents
Kyoto, Japan
SESSION: Processor-based system table of contents
Pages: 2 - 7  
Year of Publication: 2002
ISBN:1-58113-576-9
Authors
Bhuvan Middha  Indian Institute of Technology Delhi, India
Anup Gangwar  Indian Institute of Technology Delhi, India
Anshul Kumar  Indian Institute of Technology Delhi, India
M. Balakrishnan  Indian Institute of Technology Delhi, India
Paolo Ienne  Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\DATC : IEEE Computer Society
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 47,   Citation Count: 6
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ABSTRACT

It is widely accepted that use of an Application Specific Instruction Set Processor (ASIP) in an embedded system can provide a solution which is much more flexible than ASICs and much more efficient than standard processors in terms of performance and power consumption. However a lack of an acceptable design methodology and supporting tools for ASIPs limits their use even today. We present in this paper a methodology for design space exploration of high performance VLIW ASIPs by modeling Application Specific Functional Units in Trimaran Compiler Infrastructure. To demonstrate the effectiveness of our strategy we consider two important applications FFT and Kalman Filter and perform compute intensive operations in these applications via special Functional Units. The results we obtain are very promising with up to 2x speed improvement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Shail Aditya, Vinod Kathail, and B. Ramakrishna Rau. Elcor's Machine Description System: Version 3.0. Technical Report HPL-1998-128, Hewlett-Packard Laboratories, October 1998.
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Paolo Ienne, Laura Pozzi, M. Vuletic. On the Limits of Processor Specialisation by Mapping Dataflow Sections on Ad-hoc Functional Units. CS Technical Report 01/376, LAP, EPFL, Lausanne. December 2001.
 
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The Trimaran Compiler Infrastructure, http://www.trimaran.org.
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J. Gyllenhaal, B. Rau, and W. Hwu. HMDES version 2.0 specification, IMPACT, University of Illinois, Urbana, IL, Tech. Rep. IMPACT-96-03, 1996.


Collaborative Colleagues:
Bhuvan Middha: colleagues
Anup Gangwar: colleagues
Anshul Kumar: colleagues
M. Balakrishnan: colleagues
Paolo Ienne: colleagues