Activity-sensitive clock tree construction for low power

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Activity-sensitive clock tree construction for low power

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2002 international symposium on Low power electronics and design table of contents

Monterey, California, USA

SESSION: Poster Session 4 table of contents

Pages: 279 - 282

Year of Publication: 2002

ISBN:1-58113-475-4

Authors

Chunhong Chen	University of Windsor, Windsor, Canada
Changjun Kang	University of Windsor, Windsor, Canada
Majid Sarrafzadeh	University of California at Los Angeles, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 17, Citation Count: 5

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node difference between different modules to optimize the power consumption due to the interconnections (i.e., clock gating signals and clock edges). We also develop a method to determine gating signals with minimum number of transitions. After the clock tree is constructed, the gating signals are optimized for further power savings.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Tsay R. S. An exact zero-skew clock routing algorithm. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2 (February 1993), 242--249.
	2	Chao T. H., Hsu Y. C., Ho J. M., Boese K. D., and Kahng A. B. Zero skew routing with minimum wirelength. IEEE Trans. on Circuits and Systems, vol. 39, no. 11 (1992), 799--814.
	3	Edahiro M. Delay minimization for zero-skew routing. in Proceedings of ICCAD (Nov. 1993), 563--566.
	4	Farrahi A. H., Chen C. H., Sarrafzadeh M., and Tellez G. Activity-driven clock design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 6 (June 2001), 706--714.
	5	Oh J. and Pedram M. Gated clock routing for low-power microprocessor design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 6 (June 2001), 715--722.
	6	http://poppy.snu.ac.kr/ shlee/class/icda2001/CDFGTool.pdf

CITED BY 5

	Monica Donno , Alessandro Ivaldi , Luca Benini , Enrico Macii, Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Wei-Chung Chao , Wai-Kei Mak, Low-power gated and buffered clock network construction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-20, January 2008
	Weixiang Shen , Yici Cai , Xianlong Hong , Jiang Hu, Activity and register placement aware gated clock network design, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Weixiang Shen , Yici Cai , Xianlong Hong , Jiang Hu, Low Power Gated Clock Tree Driven Placement, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.2, p.595-603, February 2008