Dynamic Vt SRAM

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Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2002 international symposium on Low power electronics and design table of contents

Monterey, California, USA

SESSION: Poster Session 3 table of contents

Pages: 251 - 254

Year of Publication: 2002

ISBN:1-58113-475-4

Authors

Chris H. Kim	Purdue University, West Lafayette, IN
Kaushik Roy	Purdue University, West Lafayette, IN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 55, Citation Count: 14

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ABSTRACT

This paper presents a Dynamic V_t SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The V_t of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high V_t only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 14

	Vishal Khandelwal , Ankur Srivastava, Active mode leakage reduction using fine-grained forward body biasing strategy, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Yiran Chen , Kaushik Roy , Cheng-Kok Koh, Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.893-898, January 27-30, 2004, Yokohama, Japan
	Yiran Chen , Kaushik Roy , Cheng-Kok Koh, Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Shengqi Yang , Wayne Wolf , Wenping Wang , N. Vijaykrishnan , Yuan Xie, Low-leakage robust SRAM cell design for sub-100nm technologies, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yiran Chen , Kaushik Roy , Cheng-Kok Koh, Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.75-85, January 2005
	Bipul C. Paul , Amit Agarwal , Kaushik Roy, Low-power design techniques for scaled technologies, Integration, the VLSI Journal, v.39 n.2, p.64-89, March 2006
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Behnam Amelifard , Massoud Pedram , Farzan Fallah, Low-leakage SRAM Design with Dual V_t Transistors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.729-734, March 27-29, 2006
	Praveen Kalla , Xiaobo Sharon Hu , Jörg Henkel, LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.518, November 09-13, 2003
	Mingoo Seok , Dennis Sylvester , David Blaauw, Optimal technology selection for minimizing energy and variability in low voltage applications, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.851-860, July 2008
	Shengqi Yang , Wenping Wang , Tiehan Lu , Wayne Wolf , N. Vijaykrishnan , Yuan Xie, Case study of reliability-aware and low-power design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.861-873, July 2008
	Fabio Frustaci , Pasquale Corsonello , Stefania Perri , Giuseppe Cocorullo, Techniques for leakage energy reduction in deep submicrometer cache memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1238-1249, November 2006
	Vishal Khandelwal , Ankur Srivastava, Active mode leakage reduction using fine-grained forward body biasing strategy, Integration, the VLSI Journal, v.40 n.4, p.561-570, July, 2007