A history-based I-cache for low-energy multimedia applications

ABSTRACT

This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits program-execution footprints recorded in the Branch Target Buffer (BTB), and attempts to detect and eliminate unnecessary tag checks at run time. Simulation results show that our approach can eliminate up to 95% of tag checks, saving the cache energy by 17%, while affecting the processor performance by only 0.2%.

REFERENCES

• 1: Mediabench. In URL:http://www.cs.ucla.edu/~leec/mediabench/.
• 2: Simplescalar simulation tools for microprocessor and system evaluation. In URL:http://www.simplescalar.org/.
• 3: Energy and Performance Improvements in Microprocessor Design Using a Loop Cache, Proceedings of the 1999 IEEE International Conference on Computer Design, p.378, October 10-13, 1999
• 4: Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
• 5: K. Inoue and K. Murakami. Instruction cache architecture exploiting program execution footprints. In International Symposium on High-Performance Computer Architecture, Work-in-progress session (included in the CD proceedings), Feb. 2001.
• 6: Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
• 7: M. B. Kamble , K. Ghose, Energy-Efficiency of VLSI Caches: A Comparative Study, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.261, January 04-07, 1997
• 8: Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 9: A. Ma, M. Zhan, and K. Asanović. Way memorization to reduce fetch energy in instruction caches. In ISCA Workshop on Complexity Effective Design, July 2001.
• 10: Ramesh Panwar , David Rennels, Reducing the frequency of tag compares for low power I-cache design, Proceedings of the 1995 international symposium on Low power design, p.57-62, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224092]
• 11: S. Segars. Low power desin techniques for microprocessors. In ISSCC Tutorial, Feb. 2001.
• 12: S. Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. In WRL Research Report 93/5, July 1994.
• 13: Emmett Witchel , Sam Larsen , C. Scott Ananian , Krste Asanović, Direct addressed caches for reduced power consumption, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

General Terms:
Design