Managing leakage for transient data: decay and quasi-static 4T memory cells

ABSTRACT

Much of on-chip storage is devoted to transient, often short-lived, data. Despite this, virtually all on-chip array structures use six-transistor (6T) static RAM cells that store data indefinitely. In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings. These cells have no connection to Vdd and thus inherently provide decay functionality: values are refreshed upon access but discharge over time without use. This makes 4T cells uniquely well-suited for predictive structures like branch predictors and BTBs where data integrity is not essential. We use quantitative evaluations (both circuit-level and cycle-level) to explore the design space and quantify the opportunities. Overall, 4T-based branch predictors offer 12-33% area savings and 60-80% leakage savings with minimal performance impact. More broadly, this paper suggests a new view of how to support transient data in power-aware processors.

REFERENCES

• 1: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 2: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 3: Doug Burger , Todd M. Austin, The SimpleScalar tool set, version 2.0, ACM SIGARCH Computer Architecture News, v.25 n.3, p.13-25, June 1997 [doi>10.1145/268806.268810]
• 4: K. Diefendorff. Pentium III = Pentium II + SSE. Microprocessor Report, Mar. 8 1999.
• 5: P. Diodato et al. Embedded dram: An element and circuit evaluation. In IEEE Custom Integrated Circuits Conference, Jun 2001.
• 6: Z. Hu, P. Juang, K. Skadron, M. Martonosi, and D. Clark. Applying decay strategies to branch predictors for leakage energy savings. In Proceedings of the ICCD 2002. To appear.
• 7: Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, Proceedings of the 28th annual international symposium on Computer architecture, p.240-251, June 30-July 04, 2001, Göteborg, Sweden
• 8: Michael Powell , Se-Hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar, Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, Proceedings of the 2000 international symposium on Low power electronics and design, p.90-95, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344526]
• 9: S. Schuster, L. Terman, and R. Franch. A 4-device cmos static ram cell using sub-threshold conduction. In Symposium on VLSI Technology, Systems, and Applications, 1987.
• 10: The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.
• 11: A. G. Varadi. Quasi-static mos memory array with standby operation. US Patent Number 4,120,047.
• 12: Wayne Wolf, Modern VLSI design (2nd ed.): systems on silicon, Prentice-Hall, Inc., Upper Saddle River, NJ, 1998
• 13: Huiyang Zhou , Mark C. Toburen , Eric Rotenberg , Thomas M. Conte, Adaptive Mode Control: A Static-Power-Efficient Cache Design, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.61, September 08-12, 2001

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Measurement

Keywords:
4T, decay, leakage power, memory cell, quasi-static, transient data