| Dispatching heuristic for wafer fabrication |
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Winter Simulation Conference
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Proceedings of the 33nd conference on Winter simulation
table of contents
Arlington, Virginia
SESSION: Semiconductor manufacturing
table of contents
Pages: 1215 - 1219
Year of Publication: 2001
ISBN:0-7803-7309-X
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Authors
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Loo Hay Lee
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National University of Singapore, Kent Ridge, Singapore 119260 SINGAPORE
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Loon Ching Tang
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National University of Singapore, Kent Ridge, Singapore 119260 SINGAPORE
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Soon Chee Chan
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National University of Singapore, Kent Ridge, Singapore 119260 SINGAPORE
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 0, Downloads (12 Months): 10, Citation Count: 1
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ABSTRACT
As the semiconductor industry moves into the next millennium, companies increasingly will be faced with production obstacles that impede their ability to remain competitive. Effective equipment and line management planning will increasingly be required to maximize profitability while maintaining the flexibility to keep pace with rapidly changing manufacturing environment. In this paper, the authors present a two-bottleneck machines center model for wafer operations analysis. A new dispatching rule Balance Work Content, BWC, is introduced. This is a selective dispatching rule whereby it attempts to maximize the utilization of bottleneck machine. A systematic approach to assessing the impact of BWC is presented. Extensive simulation runs on both the deterministic and stochastic models developed shows its supremacy over conventional approaches of FIFO and SPT.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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