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Direct addressed caches for reduced power consumption
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Source International Symposium on Microarchitecture archive
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture table of contents
Austin, Texas
SESSION: Energy efficient architectures table of contents
Pages: 124 - 133  
Year of Publication: 2001
ISBN ~ ISSN:1072-4451 , 0-7695-1369-7
Authors
Emmett Witchel  MIT Laboratory for Computer Science, Cambridge, MA
Sam Larsen  MIT Laboratory for Computer Science, Cambridge, MA
C. Scott Ananian  MIT Laboratory for Computer Science, Cambridge, MA
Krste Asanović  MIT Laboratory for Computer Science, Cambridge, MA
Sponsors
: IEEE TC-MARCH
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 24,   Citation Count: 16
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ABSTRACT

A direct addressed cache is a hardware-software design for an energy-efficient microprocessor data cache. Direct addressing allows software to access cache data without a hardware cache tag check. These tag-unchecked loads and stores save the energy of a tag check when the compiler can guarantee an access will be to the same line as an earlier access. We have added support for tag-unchecked loads and stores to C and Java compilers. For Mediabench C programs, the compiler eliminates 16-76% of data cache tag accesses, with half of the benchmarks avoiding over 40% of the data tag checks. For SPECjvm98 Java programs, the compiler eliminates 18-63% of data cache tag checks. These tag check reductions translate into data cache energy savings of 9-40%, and overall processor and cache energy savings of 2-8%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Burd. Energy-Efficient Processor System Design. PhD thesis, University of California at Berkeley, 2001.
 
2
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A. Ma, M. Zhang, and K. Asanović. Way memoization to reduce fetch energy in instruction caches. ISCA Workshop on Complexity Effective Design, July 2001.
 
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C. A. Moritz, M. Frank, and S. Amarasinghe. Flex-cache: A framework for flexible compiler generated data caching. Lecture Notes of Computer Science, Springer-Verlag, 2001.
 
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M. Zhang and K. Asanović. Highly-associative caches for low-power processors. Kool Chips Workshop, MICRO-33, 2000.

CITED BY  16
Collaborative Colleagues:
Emmett Witchel: colleagues
Sam Larsen: colleagues
C. Scott Ananian: colleagues
Krste Asanović: colleagues