| Direct addressed caches for reduced power consumption |
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International Symposium on Microarchitecture
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Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
table of contents
Austin, Texas
SESSION: Energy efficient architectures
table of contents
Pages: 124 - 133
Year of Publication: 2001
ISBN ~ ISSN:1072-4451 , 0-7695-1369-7
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 16
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ABSTRACT
A direct addressed cache is a hardware-software design for an energy-efficient microprocessor data cache. Direct addressing allows software to access cache data without a hardware cache tag check. These tag-unchecked loads and stores save the energy of a tag check when the compiler can guarantee an access will be to the same line as an earlier access. We have added support for tag-unchecked loads and stores to C and Java compilers. For Mediabench C programs, the compiler eliminates 16-76% of data cache tag accesses, with half of the benchmarks avoiding over 40% of the data tag checks. For SPECjvm98 Java programs, the compiler eliminates 18-63% of data cache tag checks. These tag check reductions translate into data cache energy savings of 9-40%, and overall processor and cache energy savings of 2-8%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 16
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Osman S. Unsal , Raksit Ashok , Israel Koren , C. Mani Krishna , Csaba Andras Moritz, Cool-cache for hot multimedia, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
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Ja Chun Ku , Serkan Ozdemir , Gokhan Memik , Yehea Ismail, Power density minimization for highly-associative caches in embedded processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
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Marc Gonzàlez , Nikola Vujic , Xavier Martorell , Eduard Ayguadé , Alexandre E. Eichenberger , Tong Chen , Zehra Sura , Tao Zhang , Kevin O'Brien , Kathryn O'Brien, Hybrid access-specific software cache techniques for the cell BE architecture, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
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